73 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)  in tegra_sor_readl()  argument
75 	return readl(sor->regs + (offset << 2));  in tegra_sor_readl()
78 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,  in tegra_sor_writel()  argument
81 	writel(value, sor->regs + (offset << 2));  in tegra_sor_writel()
84 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,  in tegra_sor_dp_train_fast()  argument
97 	tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);  in tegra_sor_dp_train_fast()
103 	tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);  in tegra_sor_dp_train_fast()
109 	tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);  in tegra_sor_dp_train_fast()
112 	tegra_sor_writel(sor, 0, SOR_LVDS);  in tegra_sor_dp_train_fast()
114 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
118 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
120 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
123 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
127 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
130 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_dp_train_fast()
132 	err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);  in tegra_sor_dp_train_fast()
143 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
147 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
151 	value = tegra_sor_readl(sor, SOR_DP_SPARE_0);  in tegra_sor_dp_train_fast()
155 	tegra_sor_writel(sor, value, SOR_DP_SPARE_0);  in tegra_sor_dp_train_fast()
164 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
168 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
179 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_dp_train_fast()
183 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
190 static void tegra_sor_super_update(struct tegra_sor *sor)  in tegra_sor_super_update()  argument
192 	tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
193 	tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
194 	tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);  in tegra_sor_super_update()
197 static void tegra_sor_update(struct tegra_sor *sor)  in tegra_sor_update()  argument
199 	tegra_sor_writel(sor, 0, SOR_STATE_0);  in tegra_sor_update()
200 	tegra_sor_writel(sor, 1, SOR_STATE_0);  in tegra_sor_update()
201 	tegra_sor_writel(sor, 0, SOR_STATE_0);  in tegra_sor_update()
204 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)  in tegra_sor_setup_pwm()  argument
208 	value = tegra_sor_readl(sor, SOR_PWM_DIV);  in tegra_sor_setup_pwm()
211 	tegra_sor_writel(sor, value, SOR_PWM_DIV);  in tegra_sor_setup_pwm()
213 	value = tegra_sor_readl(sor, SOR_PWM_CTL);  in tegra_sor_setup_pwm()
218 	tegra_sor_writel(sor, value, SOR_PWM_CTL);  in tegra_sor_setup_pwm()
223 		value = tegra_sor_readl(sor, SOR_PWM_CTL);  in tegra_sor_setup_pwm()
233 static int tegra_sor_attach(struct tegra_sor *sor)  in tegra_sor_attach()  argument
238 	value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);  in tegra_sor_attach()
241 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_attach()
242 	tegra_sor_super_update(sor);  in tegra_sor_attach()
245 	value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);  in tegra_sor_attach()
247 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_attach()
248 	tegra_sor_super_update(sor);  in tegra_sor_attach()
253 		value = tegra_sor_readl(sor, SOR_TEST);  in tegra_sor_attach()
263 static int tegra_sor_wakeup(struct tegra_sor *sor)  in tegra_sor_wakeup()  argument
271 		value = tegra_sor_readl(sor, SOR_TEST);  in tegra_sor_wakeup()
283 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)  in tegra_sor_power_up()  argument
287 	value = tegra_sor_readl(sor, SOR_PWR);  in tegra_sor_power_up()
289 	tegra_sor_writel(sor, value, SOR_PWR);  in tegra_sor_power_up()
294 		value = tegra_sor_readl(sor, SOR_PWR);  in tegra_sor_power_up()
319 static int tegra_sor_compute_params(struct tegra_sor *sor,  in tegra_sor_compute_params()  argument
387 static int tegra_sor_calc_config(struct tegra_sor *sor,  in tegra_sor_calc_config()  argument
416 		if (tegra_sor_compute_params(sor, &params, i))  in tegra_sor_calc_config()
435 	dev_dbg(sor->dev,  in tegra_sor_calc_config()
450 		dev_err(sor->dev,  in tegra_sor_calc_config()
455 		dev_err(sor->dev, "watermark too high, forcing to %u\n",  in tegra_sor_calc_config()
473 	dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,  in tegra_sor_calc_config()
479 static int tegra_sor_detach(struct tegra_sor *sor)  in tegra_sor_detach()  argument
484 	value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);  in tegra_sor_detach()
486 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
487 	tegra_sor_super_update(sor);  in tegra_sor_detach()
492 		value = tegra_sor_readl(sor, SOR_PWR);  in tegra_sor_detach()
501 	value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);  in tegra_sor_detach()
503 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
504 	tegra_sor_super_update(sor);  in tegra_sor_detach()
507 	value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);  in tegra_sor_detach()
509 	tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);  in tegra_sor_detach()
510 	tegra_sor_super_update(sor);  in tegra_sor_detach()
515 		value = tegra_sor_readl(sor, SOR_TEST);  in tegra_sor_detach()
528 static int tegra_sor_power_down(struct tegra_sor *sor)  in tegra_sor_power_down()  argument
533 	value = tegra_sor_readl(sor, SOR_PWR);  in tegra_sor_power_down()
536 	tegra_sor_writel(sor, value, SOR_PWR);  in tegra_sor_power_down()
541 		value = tegra_sor_readl(sor, SOR_PWR);  in tegra_sor_power_down()
551 	err = clk_set_parent(sor->clk, sor->clk_safe);  in tegra_sor_power_down()
553 		dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);  in tegra_sor_power_down()
555 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_power_down()
558 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_power_down()
563 	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);  in tegra_sor_power_down()
568 		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);  in tegra_sor_power_down()
578 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_power_down()
580 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_power_down()
584 	value = tegra_sor_readl(sor, SOR_PLL_0);  in tegra_sor_power_down()
587 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_power_down()
589 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_power_down()
592 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_power_down()
611 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)  in tegra_sor_crc_wait()  argument
618 		value = tegra_sor_readl(sor, SOR_CRC_A);  in tegra_sor_crc_wait()
631 	struct tegra_sor *sor = file->private_data;  in tegra_sor_crc_read()  local
636 	mutex_lock(&sor->lock);  in tegra_sor_crc_read()
638 	if (!sor->enabled) {  in tegra_sor_crc_read()
643 	value = tegra_sor_readl(sor, SOR_STATE_1);  in tegra_sor_crc_read()
645 	tegra_sor_writel(sor, value, SOR_STATE_1);  in tegra_sor_crc_read()
647 	value = tegra_sor_readl(sor, SOR_CRC_CNTRL);  in tegra_sor_crc_read()
649 	tegra_sor_writel(sor, value, SOR_CRC_CNTRL);  in tegra_sor_crc_read()
651 	value = tegra_sor_readl(sor, SOR_TEST);  in tegra_sor_crc_read()
653 	tegra_sor_writel(sor, value, SOR_TEST);  in tegra_sor_crc_read()
655 	err = tegra_sor_crc_wait(sor, 100);  in tegra_sor_crc_read()
659 	tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);  in tegra_sor_crc_read()
660 	value = tegra_sor_readl(sor, SOR_CRC_B);  in tegra_sor_crc_read()
667 	mutex_unlock(&sor->lock);  in tegra_sor_crc_read()
681 	struct tegra_sor *sor = node->info_ent->data;  in tegra_sor_show_regs()  local
685 		   tegra_sor_readl(sor, name))  in tegra_sor_show_regs()
811 static int tegra_sor_debugfs_init(struct tegra_sor *sor,  in tegra_sor_debugfs_init()  argument
818 	sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);  in tegra_sor_debugfs_init()
819 	if (!sor->debugfs)  in tegra_sor_debugfs_init()
822 	sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),  in tegra_sor_debugfs_init()
824 	if (!sor->debugfs_files) {  in tegra_sor_debugfs_init()
830 		sor->debugfs_files[i].data = sor;  in tegra_sor_debugfs_init()
832 	err = drm_debugfs_create_files(sor->debugfs_files,  in tegra_sor_debugfs_init()
834 				       sor->debugfs, minor);  in tegra_sor_debugfs_init()
838 	entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,  in tegra_sor_debugfs_init()
848 	kfree(sor->debugfs_files);  in tegra_sor_debugfs_init()
849 	sor->debugfs_files = NULL;  in tegra_sor_debugfs_init()
851 	debugfs_remove_recursive(sor->debugfs);  in tegra_sor_debugfs_init()
852 	sor->debugfs = NULL;  in tegra_sor_debugfs_init()
856 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)  in tegra_sor_debugfs_exit()  argument
858 	drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),  in tegra_sor_debugfs_exit()
859 				 sor->minor);  in tegra_sor_debugfs_exit()
860 	sor->minor = NULL;  in tegra_sor_debugfs_exit()
862 	kfree(sor->debugfs_files);  in tegra_sor_debugfs_exit()
863 	sor->debugfs = NULL;  in tegra_sor_debugfs_exit()
865 	debugfs_remove_recursive(sor->debugfs);  in tegra_sor_debugfs_exit()
866 	sor->debugfs_files = NULL;  in tegra_sor_debugfs_exit()
877 	struct tegra_sor *sor = to_sor(output);  in tegra_sor_connector_detect()  local
879 	if (sor->dpaux)  in tegra_sor_connector_detect()
880 		return tegra_dpaux_detect(sor->dpaux);  in tegra_sor_connector_detect()
898 	struct tegra_sor *sor = to_sor(output);  in tegra_sor_connector_get_modes()  local
901 	if (sor->dpaux)  in tegra_sor_connector_get_modes()
902 		tegra_dpaux_enable(sor->dpaux);  in tegra_sor_connector_get_modes()
906 	if (sor->dpaux)  in tegra_sor_connector_get_modes()
907 		tegra_dpaux_disable(sor->dpaux);  in tegra_sor_connector_get_modes()
948 	struct tegra_sor *sor = to_sor(output);  in tegra_sor_encoder_mode_set()  local
955 	mutex_lock(&sor->lock);  in tegra_sor_encoder_mode_set()
957 	if (sor->enabled)  in tegra_sor_encoder_mode_set()
960 	err = clk_prepare_enable(sor->clk);  in tegra_sor_encoder_mode_set()
964 	reset_control_deassert(sor->rst);  in tegra_sor_encoder_mode_set()
970 	aux = (struct drm_dp_aux *)sor->dpaux;  in tegra_sor_encoder_mode_set()
972 	if (sor->dpaux) {  in tegra_sor_encoder_mode_set()
973 		err = tegra_dpaux_enable(sor->dpaux);  in tegra_sor_encoder_mode_set()
975 			dev_err(sor->dev, "failed to enable DP: %d\n", err);  in tegra_sor_encoder_mode_set()
979 			dev_err(sor->dev, "failed to probe eDP link: %d\n",  in tegra_sor_encoder_mode_set()
985 	err = clk_set_parent(sor->clk, sor->clk_safe);  in tegra_sor_encoder_mode_set()
987 		dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);  in tegra_sor_encoder_mode_set()
992 	err = tegra_sor_calc_config(sor, mode, &config, &link);  in tegra_sor_encoder_mode_set()
994 		dev_err(sor->dev, "failed to compute link configuration: %d\n",  in tegra_sor_encoder_mode_set()
997 	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1000 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1002 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1004 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1007 	value = tegra_sor_readl(sor, SOR_PLL_3);  in tegra_sor_encoder_mode_set()
1009 	tegra_sor_writel(sor, value, SOR_PLL_3);  in tegra_sor_encoder_mode_set()
1013 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1015 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1019 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1022 	tegra_sor_writel(sor, value, SOR_PLL_1);  in tegra_sor_encoder_mode_set()
1025 		value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1032 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1035 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1042 	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1045 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1048 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1051 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1053 	value = tegra_sor_readl(sor, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1055 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1057 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1059 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1064 		dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);  in tegra_sor_encoder_mode_set()
1071 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1073 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1078 	value = tegra_sor_readl(sor, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1081 	tegra_sor_writel(sor, value, SOR_PLL_0);  in tegra_sor_encoder_mode_set()
1083 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1085 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1090 	value = tegra_sor_readl(sor, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1092 	tegra_sor_writel(sor, value, SOR_PLL_2);  in tegra_sor_encoder_mode_set()
1095 	err = clk_set_parent(sor->clk, sor->clk_dp);  in tegra_sor_encoder_mode_set()
1097 		dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);  in tegra_sor_encoder_mode_set()
1100 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1117 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1119 	value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1122 	tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1127 	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);  in tegra_sor_encoder_mode_set()
1130 		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);  in tegra_sor_encoder_mode_set()
1138 	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1141 	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1144 	value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1151 	tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1160 	tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_encoder_mode_set()
1162 	value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);  in tegra_sor_encoder_mode_set()
1179 	tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);  in tegra_sor_encoder_mode_set()
1181 	value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1184 	tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1186 	value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1189 	tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);  in tegra_sor_encoder_mode_set()
1192 	value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1194 	tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);  in tegra_sor_encoder_mode_set()
1196 	if (sor->dpaux) {  in tegra_sor_encoder_mode_set()
1201 			dev_err(sor->dev, "failed to probe eDP link: %d\n",  in tegra_sor_encoder_mode_set()
1208 			dev_err(sor->dev, "failed to power up eDP link: %d\n",  in tegra_sor_encoder_mode_set()
1215 			dev_err(sor->dev, "failed to configure eDP link: %d\n",  in tegra_sor_encoder_mode_set()
1223 		value = tegra_sor_readl(sor, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1226 		tegra_sor_writel(sor, value, SOR_CLK_CNTRL);  in tegra_sor_encoder_mode_set()
1228 		value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1235 		tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);  in tegra_sor_encoder_mode_set()
1246 		tegra_sor_writel(sor, value, SOR_DP_TPG);  in tegra_sor_encoder_mode_set()
1248 		err = tegra_sor_dp_train_fast(sor, &link);  in tegra_sor_encoder_mode_set()
1250 			dev_err(sor->dev, "DP fast link training failed: %d\n",  in tegra_sor_encoder_mode_set()
1255 		dev_dbg(sor->dev, "fast link training succeeded\n");  in tegra_sor_encoder_mode_set()
1258 	err = tegra_sor_power_up(sor, 250);  in tegra_sor_encoder_mode_set()
1260 		dev_err(sor->dev, "failed to power up SOR: %d\n", err);  in tegra_sor_encoder_mode_set()
1298 	tegra_sor_writel(sor, value, SOR_STATE_1);  in tegra_sor_encoder_mode_set()
1306 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));  in tegra_sor_encoder_mode_set()
1312 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));  in tegra_sor_encoder_mode_set()
1318 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));  in tegra_sor_encoder_mode_set()
1324 	tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));  in tegra_sor_encoder_mode_set()
1329 	tegra_sor_writel(sor, value, SOR_CSTM);  in tegra_sor_encoder_mode_set()
1332 	err = tegra_sor_setup_pwm(sor, 250);  in tegra_sor_encoder_mode_set()
1334 		dev_err(sor->dev, "failed to setup PWM: %d\n", err);  in tegra_sor_encoder_mode_set()
1338 	tegra_sor_update(sor);  in tegra_sor_encoder_mode_set()
1346 	err = tegra_sor_attach(sor);  in tegra_sor_encoder_mode_set()
1348 		dev_err(sor->dev, "failed to attach SOR: %d\n", err);  in tegra_sor_encoder_mode_set()
1352 	err = tegra_sor_wakeup(sor);  in tegra_sor_encoder_mode_set()
1354 		dev_err(sor->dev, "failed to enable DC: %d\n", err);  in tegra_sor_encoder_mode_set()
1361 	sor->enabled = true;  in tegra_sor_encoder_mode_set()
1364 	mutex_unlock(&sor->lock);  in tegra_sor_encoder_mode_set()
1371 	struct tegra_sor *sor = to_sor(output);  in tegra_sor_encoder_disable()  local
1375 	mutex_lock(&sor->lock);  in tegra_sor_encoder_disable()
1377 	if (!sor->enabled)  in tegra_sor_encoder_disable()
1383 	err = tegra_sor_detach(sor);  in tegra_sor_encoder_disable()
1385 		dev_err(sor->dev, "failed to detach SOR: %d\n", err);  in tegra_sor_encoder_disable()
1389 	tegra_sor_writel(sor, 0, SOR_STATE_1);  in tegra_sor_encoder_disable()
1390 	tegra_sor_update(sor);  in tegra_sor_encoder_disable()
1404 	err = tegra_sor_power_down(sor);  in tegra_sor_encoder_disable()
1406 		dev_err(sor->dev, "failed to power down SOR: %d\n", err);  in tegra_sor_encoder_disable()
1410 	if (sor->dpaux) {  in tegra_sor_encoder_disable()
1411 		err = tegra_dpaux_disable(sor->dpaux);  in tegra_sor_encoder_disable()
1413 			dev_err(sor->dev, "failed to disable DP: %d\n", err);  in tegra_sor_encoder_disable()
1420 		dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);  in tegra_sor_encoder_disable()
1427 	clk_disable_unprepare(sor->clk);  in tegra_sor_encoder_disable()
1428 	reset_control_assert(sor->rst);  in tegra_sor_encoder_disable()
1430 	sor->enabled = false;  in tegra_sor_encoder_disable()
1433 	mutex_unlock(&sor->lock);  in tegra_sor_encoder_disable()
1444 	struct tegra_sor *sor = to_sor(output);  in tegra_sor_encoder_atomic_check()  local
1447 	err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,  in tegra_sor_encoder_atomic_check()
1469 	struct tegra_sor *sor = host1x_client_to_sor(client);  in tegra_sor_init()  local
1472 	if (!sor->dpaux)  in tegra_sor_init()
1475 	sor->output.dev = sor->dev;  in tegra_sor_init()
1477 	drm_connector_init(drm, &sor->output.connector,  in tegra_sor_init()
1480 	drm_connector_helper_add(&sor->output.connector,  in tegra_sor_init()
1482 	sor->output.connector.dpms = DRM_MODE_DPMS_OFF;  in tegra_sor_init()
1484 	drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,  in tegra_sor_init()
1486 	drm_encoder_helper_add(&sor->output.encoder,  in tegra_sor_init()
1489 	drm_mode_connector_attach_encoder(&sor->output.connector,  in tegra_sor_init()
1490 					  &sor->output.encoder);  in tegra_sor_init()
1491 	drm_connector_register(&sor->output.connector);  in tegra_sor_init()
1493 	err = tegra_output_init(drm, &sor->output);  in tegra_sor_init()
1499 	sor->output.encoder.possible_crtcs = 0x3;  in tegra_sor_init()
1502 		err = tegra_sor_debugfs_init(sor, drm->primary);  in tegra_sor_init()
1504 			dev_err(sor->dev, "debugfs setup failed: %d\n", err);  in tegra_sor_init()
1507 	if (sor->dpaux) {  in tegra_sor_init()
1508 		err = tegra_dpaux_attach(sor->dpaux, &sor->output);  in tegra_sor_init()
1510 			dev_err(sor->dev, "failed to attach DP: %d\n", err);  in tegra_sor_init()
1519 	err = reset_control_assert(sor->rst);  in tegra_sor_init()
1521 		dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);  in tegra_sor_init()
1525 	err = clk_prepare_enable(sor->clk);  in tegra_sor_init()
1527 		dev_err(sor->dev, "failed to enable clock: %d\n", err);  in tegra_sor_init()
1533 	err = reset_control_deassert(sor->rst);  in tegra_sor_init()
1535 		dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);  in tegra_sor_init()
1539 	err = clk_prepare_enable(sor->clk_safe);  in tegra_sor_init()
1543 	err = clk_prepare_enable(sor->clk_dp);  in tegra_sor_init()
1552 	struct tegra_sor *sor = host1x_client_to_sor(client);  in tegra_sor_exit()  local
1555 	tegra_output_exit(&sor->output);  in tegra_sor_exit()
1557 	if (sor->dpaux) {  in tegra_sor_exit()
1558 		err = tegra_dpaux_detach(sor->dpaux);  in tegra_sor_exit()
1560 			dev_err(sor->dev, "failed to detach DP: %d\n", err);  in tegra_sor_exit()
1565 	clk_disable_unprepare(sor->clk_safe);  in tegra_sor_exit()
1566 	clk_disable_unprepare(sor->clk_dp);  in tegra_sor_exit()
1567 	clk_disable_unprepare(sor->clk);  in tegra_sor_exit()
1570 		tegra_sor_debugfs_exit(sor);  in tegra_sor_exit()
1583 	struct tegra_sor *sor;  in tegra_sor_probe()  local
1587 	sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);  in tegra_sor_probe()
1588 	if (!sor)  in tegra_sor_probe()
1591 	sor->output.dev = sor->dev = &pdev->dev;  in tegra_sor_probe()
1595 		sor->dpaux = tegra_dpaux_find_by_of_node(np);  in tegra_sor_probe()
1598 		if (!sor->dpaux)  in tegra_sor_probe()
1602 	err = tegra_output_probe(&sor->output);  in tegra_sor_probe()
1607 	sor->regs = devm_ioremap_resource(&pdev->dev, regs);  in tegra_sor_probe()
1608 	if (IS_ERR(sor->regs))  in tegra_sor_probe()
1609 		return PTR_ERR(sor->regs);  in tegra_sor_probe()
1611 	sor->rst = devm_reset_control_get(&pdev->dev, "sor");  in tegra_sor_probe()
1612 	if (IS_ERR(sor->rst))  in tegra_sor_probe()
1613 		return PTR_ERR(sor->rst);  in tegra_sor_probe()
1615 	sor->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_sor_probe()
1616 	if (IS_ERR(sor->clk))  in tegra_sor_probe()
1617 		return PTR_ERR(sor->clk);  in tegra_sor_probe()
1619 	sor->clk_parent = devm_clk_get(&pdev->dev, "parent");  in tegra_sor_probe()
1620 	if (IS_ERR(sor->clk_parent))  in tegra_sor_probe()
1621 		return PTR_ERR(sor->clk_parent);  in tegra_sor_probe()
1623 	sor->clk_safe = devm_clk_get(&pdev->dev, "safe");  in tegra_sor_probe()
1624 	if (IS_ERR(sor->clk_safe))  in tegra_sor_probe()
1625 		return PTR_ERR(sor->clk_safe);  in tegra_sor_probe()
1627 	sor->clk_dp = devm_clk_get(&pdev->dev, "dp");  in tegra_sor_probe()
1628 	if (IS_ERR(sor->clk_dp))  in tegra_sor_probe()
1629 		return PTR_ERR(sor->clk_dp);  in tegra_sor_probe()
1631 	INIT_LIST_HEAD(&sor->client.list);  in tegra_sor_probe()
1632 	sor->client.ops = &sor_client_ops;  in tegra_sor_probe()
1633 	sor->client.dev = &pdev->dev;  in tegra_sor_probe()
1635 	mutex_init(&sor->lock);  in tegra_sor_probe()
1637 	err = host1x_client_register(&sor->client);  in tegra_sor_probe()
1644 	platform_set_drvdata(pdev, sor);  in tegra_sor_probe()
1651 	struct tegra_sor *sor = platform_get_drvdata(pdev);  in tegra_sor_remove()  local
1654 	err = host1x_client_unregister(&sor->client);  in tegra_sor_remove()
1661 	tegra_output_remove(&sor->output);  in tegra_sor_remove()