85 				   struct drm_dp_link *link)  in tegra_sor_dp_train_fast()  argument
136 	for (i = 0, value = 0; i < link->num_lanes; i++) {  in tegra_sor_dp_train_fast()
147 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
157 	for (i = 0, value = 0; i < link->num_lanes; i++) {  in tegra_sor_dp_train_fast()
168 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
172 	for (i = 0, value = 0; i < link->num_lanes; i++) {  in tegra_sor_dp_train_fast()
183 	err = tegra_dpaux_train(sor->dpaux, link, pattern);  in tegra_sor_dp_train_fast()
390 				 struct drm_dp_link *link)  in tegra_sor_calc_config()  argument
392 	const u64 f = 100000, link_rate = link->rate * 1000;  in tegra_sor_calc_config()
399 	if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)  in tegra_sor_calc_config()
402 	output = link_rate * 8 * link->num_lanes;  in tegra_sor_calc_config()
446 			    (link->num_lanes * 8);  in tegra_sor_calc_config()
463 	if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)  in tegra_sor_calc_config()
466 	config->hblank_symbols -= 12 / link->num_lanes;  in tegra_sor_calc_config()
471 	config->vblank_symbols -= 36 / link->num_lanes + 4;  in tegra_sor_calc_config()
950 	struct drm_dp_link link;  in tegra_sor_encoder_mode_set()  local
977 		err = drm_dp_link_probe(aux, &link);  in tegra_sor_encoder_mode_set()
992 	err = tegra_sor_calc_config(sor, mode, &config, &link);  in tegra_sor_encoder_mode_set()
1102 	if (link.num_lanes <= 2)  in tegra_sor_encoder_mode_set()
1107 	if (link.num_lanes <= 1)  in tegra_sor_encoder_mode_set()
1112 	if (link.num_lanes == 0)  in tegra_sor_encoder_mode_set()
1121 	value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);  in tegra_sor_encoder_mode_set()
1140 	value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;  in tegra_sor_encoder_mode_set()
1199 		err = drm_dp_link_probe(aux, &link);  in tegra_sor_encoder_mode_set()
1206 		err = drm_dp_link_power_up(aux, &link);  in tegra_sor_encoder_mode_set()
1213 		err = drm_dp_link_configure(aux, &link);  in tegra_sor_encoder_mode_set()
1220 		rate = drm_dp_link_rate_to_bw_code(link.rate);  in tegra_sor_encoder_mode_set()
1221 		lanes = link.num_lanes;  in tegra_sor_encoder_mode_set()
1232 		if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)  in tegra_sor_encoder_mode_set()
1239 		for (i = 0; i < link.num_lanes; i++) {  in tegra_sor_encoder_mode_set()
1248 		err = tegra_sor_dp_train_fast(sor, &link);  in tegra_sor_encoder_mode_set()