Lines Matching refs:dc
839 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_hdmi_encoder_mode_set() local
873 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_mode_set()
875 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888, in tegra_hdmi_encoder_mode_set()
881 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_mode_set()
885 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_mode_set()
888 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_mode_set()
894 if (dc->pipe) in tegra_hdmi_encoder_mode_set()
1029 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_mode_set()
1031 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_mode_set()
1033 tegra_dc_commit(dc); in tegra_hdmi_encoder_mode_set()
1040 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_hdmi_encoder_disable() local
1047 if (dc) { in tegra_hdmi_encoder_disable()
1048 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1050 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1052 tegra_dc_commit(dc); in tegra_hdmi_encoder_disable()
1062 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_hdmi_encoder_atomic_check() local
1067 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, in tegra_hdmi_encoder_atomic_check()