127 	u32 tmp;  in vtg_set_mode()  local
135 	tmp = (mode->vtotal - mode->vsync_start + 1) << 16;  in vtg_set_mode()
136 	tmp |= mode->htotal - mode->hsync_start;  in vtg_set_mode()
137 	writel(tmp, vtg->regs + VTG_VID_TFO);  in vtg_set_mode()
138 	writel(tmp, vtg->regs + VTG_VID_BFO);  in vtg_set_mode()
140 	tmp = (mode->vdisplay + mode->vtotal - mode->vsync_start + 1) << 16;  in vtg_set_mode()
141 	tmp |= mode->hdisplay + mode->htotal - mode->hsync_start;  in vtg_set_mode()
142 	writel(tmp, vtg->regs + VTG_VID_TFS);  in vtg_set_mode()
143 	writel(tmp, vtg->regs + VTG_VID_BFS);  in vtg_set_mode()
146 	tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;  in vtg_set_mode()
147 	tmp |= HDMI_DELAY;  in vtg_set_mode()
148 	writel(tmp, vtg->regs + VTG_H_HD_1);  in vtg_set_mode()
150 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
151 	tmp |= 1;  in vtg_set_mode()
152 	writel(tmp, vtg->regs + VTG_TOP_V_VD_1);  in vtg_set_mode()
153 	writel(tmp, vtg->regs + VTG_BOT_V_VD_1);  in vtg_set_mode()
158 	tmp = (mode->hsync_end - mode->hsync_start) << 16;  in vtg_set_mode()
159 	writel(tmp, vtg->regs + VTG_H_HD_2);  in vtg_set_mode()
161 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
162 	tmp |= 1;  in vtg_set_mode()
163 	writel(tmp, vtg->regs + VTG_TOP_V_VD_2);  in vtg_set_mode()
164 	writel(tmp, vtg->regs + VTG_BOT_V_VD_2);  in vtg_set_mode()
169 	tmp = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16;  in vtg_set_mode()
170 	tmp |= mode->htotal + AWG_DELAY_HD;  in vtg_set_mode()
171 	writel(tmp, vtg->regs + VTG_H_HD_3);  in vtg_set_mode()
173 	tmp = (mode->vsync_end - mode->vsync_start) << 16;  in vtg_set_mode()
174 	tmp |= mode->vtotal;  in vtg_set_mode()
175 	writel(tmp, vtg->regs + VTG_TOP_V_VD_3);  in vtg_set_mode()
176 	writel(tmp, vtg->regs + VTG_BOT_V_VD_3);  in vtg_set_mode()
178 	tmp = (mode->htotal + AWG_DELAY_HD) << 16;  in vtg_set_mode()
179 	tmp |= mode->htotal + AWG_DELAY_HD;  in vtg_set_mode()
180 	writel(tmp, vtg->regs + VTG_TOP_V_HD_3);  in vtg_set_mode()
181 	writel(tmp, vtg->regs + VTG_BOT_V_HD_3);  in vtg_set_mode()
184 	tmp = (mode->hsync_end - mode->hsync_start) << 16;  in vtg_set_mode()
185 	writel(tmp, vtg->regs + VTG_H_HD_4);  in vtg_set_mode()
187 	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;  in vtg_set_mode()
188 	tmp |= 1;  in vtg_set_mode()
189 	writel(tmp, vtg->regs + VTG_TOP_V_VD_4);  in vtg_set_mode()
190 	writel(tmp, vtg->regs + VTG_BOT_V_VD_4);  in vtg_set_mode()