Lines Matching refs:mode

110 	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;  in rcar_du_crtc_set_display_timing()  local
111 unsigned long mode_clock = mode->clock * 1000; in rcar_du_crtc_set_display_timing()
151 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL) in rcar_du_crtc_set_display_timing()
152 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL) in rcar_du_crtc_set_display_timing()
157 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); in rcar_du_crtc_set_display_timing()
158 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + in rcar_du_crtc_set_display_timing()
159 mode->hdisplay - 19); in rcar_du_crtc_set_display_timing()
160 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - in rcar_du_crtc_set_display_timing()
161 mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
162 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); in rcar_du_crtc_set_display_timing()
164 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
165 mode->crtc_vsync_end - 2); in rcar_du_crtc_set_display_timing()
166 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
167 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
168 mode->crtc_vdisplay - 2); in rcar_du_crtc_set_display_timing()
169 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
170 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
171 mode->crtc_vsync_start - 1); in rcar_du_crtc_set_display_timing()
172 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); in rcar_du_crtc_set_display_timing()
174 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start); in rcar_du_crtc_set_display_timing()
175 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); in rcar_du_crtc_set_display_timing()
376 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; in rcar_du_crtc_start()
474 const struct drm_display_mode *mode, in rcar_du_crtc_mode_fixup() argument