Lines Matching refs:addr
43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit() local
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit() local
80 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v2_2_semaphore_emit()
83 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v2_2_semaphore_emit()
100 uint64_t addr; in uvd_v2_2_resume() local
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v2_2_resume()
118 addr += size; in uvd_v2_2_resume()
120 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v2_2_resume()
123 addr += size; in uvd_v2_2_resume()
125 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v2_2_resume()
129 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
130 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v2_2_resume()
133 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
134 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v2_2_resume()