39 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,  in uvd_v1_0_get_rptr()  argument
53 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,  in uvd_v1_0_get_wptr()  argument
67 void uvd_v1_0_set_wptr(struct radeon_device *rdev,  in uvd_v1_0_set_wptr()  argument
81 void uvd_v1_0_fence_emit(struct radeon_device *rdev,  in uvd_v1_0_fence_emit()  argument
84 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in uvd_v1_0_fence_emit()
85 	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;  in uvd_v1_0_fence_emit()
110 int uvd_v1_0_resume(struct radeon_device *rdev)  in uvd_v1_0_resume()  argument
116 	r = radeon_uvd_resume(rdev);  in uvd_v1_0_resume()
121 	addr = (rdev->uvd.gpu_addr >> 3) + 16;  in uvd_v1_0_resume()
122 	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;  in uvd_v1_0_resume()
137 	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v1_0_resume()
141 	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v1_0_resume()
144 	WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));  in uvd_v1_0_resume()
156 int uvd_v1_0_init(struct radeon_device *rdev)  in uvd_v1_0_init()  argument
158 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_init()
163 	if (rdev->family < CHIP_RV740)  in uvd_v1_0_init()
164 		radeon_set_uvd_clocks(rdev, 10000, 10000);  in uvd_v1_0_init()
166 		radeon_set_uvd_clocks(rdev, 53300, 40000);  in uvd_v1_0_init()
168 	r = uvd_v1_0_start(rdev);  in uvd_v1_0_init()
173 	r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);  in uvd_v1_0_init()
179 	r = radeon_ring_lock(rdev, ring, 10);  in uvd_v1_0_init()
204 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_init()
208 	radeon_set_uvd_clocks(rdev, 0, 0);  in uvd_v1_0_init()
211 		switch (rdev->family) {  in uvd_v1_0_init()
247 void uvd_v1_0_fini(struct radeon_device *rdev)  in uvd_v1_0_fini()  argument
249 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_fini()
251 	uvd_v1_0_stop(rdev);  in uvd_v1_0_fini()
262 int uvd_v1_0_start(struct radeon_device *rdev)  in uvd_v1_0_start()  argument
264 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_start()
390 void uvd_v1_0_stop(struct radeon_device *rdev)  in uvd_v1_0_stop()  argument
420 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ring_test()  argument
427 	r = radeon_ring_lock(rdev, ring, 3);  in uvd_v1_0_ring_test()
435 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_ring_test()
436 	for (i = 0; i < rdev->usec_timeout; i++) {  in uvd_v1_0_ring_test()
443 	if (i < rdev->usec_timeout) {  in uvd_v1_0_ring_test()
464 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,  in uvd_v1_0_semaphore_emit()  argument
481 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)  in uvd_v1_0_ib_execute()  argument
483 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in uvd_v1_0_ib_execute()
499 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ib_test()  argument
504 	if (rdev->family < CHIP_RV740)  in uvd_v1_0_ib_test()
505 		r = radeon_set_uvd_clocks(rdev, 10000, 10000);  in uvd_v1_0_ib_test()
507 		r = radeon_set_uvd_clocks(rdev, 53300, 40000);  in uvd_v1_0_ib_test()
513 	r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);  in uvd_v1_0_ib_test()
519 	r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);  in uvd_v1_0_ib_test()
533 	radeon_set_uvd_clocks(rdev, 0, 0);  in uvd_v1_0_ib_test()