Lines Matching refs:u32
32 u32 sclk;
33 u32 vddc_index;
34 u32 ds_divider_index;
35 u32 ss_divider_index;
36 u32 allow_gnb_slow;
37 u32 sclk_dpm_tdp_limit;
46 u32 num_levels;
48 u32 flags;
55 u32 num_max_voltage_levels;
56 u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
65 u32 num_entries;
70 u32 sclk_frequency;
76 u32 num_max_dpm_entries;
81 u32 bootup_sclk;
82 u32 min_sclk;
83 u32 bootup_uma_clk;
90 u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
91 u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
92 u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
93 u32 sclk_dpm_boost_margin;
94 u32 sclk_dpm_throttle_margin;
95 u32 sclk_dpm_tdp_limit_pg;
96 u32 gnb_tdp_limit;
97 u32 sclk_dpm_tdp_limit_boost;
98 u32 boost_sclk;
99 u32 boost_vid_2bit;
104 u32 asi;
105 u32 pasi;
106 u32 bsp;
107 u32 bsu;
108 u32 pbsp;
109 u32 pbsu;
110 u32 dsp;
111 u32 psp;
112 u32 thermal_auto_throttling;
113 u32 uvd_m3_arbiter;
114 u32 fw_version;
192 void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
202 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
204 u32 vid_2bit);
205 u32 sumo_get_sleep_divider_from_id(u32 id);
206 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
207 u32 sclk,
208 u32 min_sclk_in_sr);
213 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
218 u32 sumo_get_running_fw_version(struct radeon_device *rdev);