Lines Matching refs:uint32_t

40     uint32_t        RefClockFrequency;
41     uint32_t        PmTimerP;
42     uint32_t        FeatureEnables;
43     uint32_t        PreVBlankGap;
44     uint32_t        VBlankTimeout;
45     uint32_t        TrainTimeGap;
47     uint32_t        MvddSwitchTime;
48     uint32_t        LongestAcpiTrainTime;
49     uint32_t        AcpiDelay;
50     uint32_t        G5TrainTime;
51     uint32_t        DelayMpllPwron;
52     uint32_t        VoltageChangeTimeout;
53     uint32_t        HandshakeDisables;
65     uint32_t        AverageGraphicsA;
66     uint32_t        AverageMemoryA;
67     uint32_t        AverageGioA;
79     uint32_t        DRAM_LOG_ADDR_H;
80     uint32_t        DRAM_LOG_ADDR_L;
81     uint32_t        DRAM_LOG_PHY_ADDR_H;
82     uint32_t        DRAM_LOG_PHY_ADDR_L;
83     uint32_t        DRAM_LOG_BUFF_SIZE;
84     uint32_t        UlvEnterC;
85     uint32_t        UlvTime;
86     uint32_t        Reserved[3];
105     uint32_t    Flags;
106     uint32_t    MinVddc;
107     uint32_t    MinVddcPhases;
109     uint32_t    SclkFrequency;
114     uint32_t    CgSpllFuncCntl3;
115     uint32_t    CgSpllFuncCntl4;
116     uint32_t    SpllSpreadSpectrum;
117     uint32_t    SpllSpreadSpectrum2;
118     uint32_t    CcPwrDynRm;
119     uint32_t    CcPwrDynRm1;
136     uint32_t    Flags;
137     uint32_t    MinVddc;
138     uint32_t    MinVddcPhases;
139     uint32_t    SclkFrequency;
144     uint32_t    CgSpllFuncCntl;
145     uint32_t    CgSpllFuncCntl2;
146     uint32_t    CgSpllFuncCntl3;
147     uint32_t    CgSpllFuncCntl4;
148     uint32_t    SpllSpreadSpectrum;
149     uint32_t    SpllSpreadSpectrum2;
150     uint32_t    CcPwrDynRm;
151     uint32_t    CcPwrDynRm1;
158     uint32_t    CcPwrDynRm;
159     uint32_t    CcPwrDynRm1;
163     uint32_t    Reserved;
170     uint32_t    MinVddc;
171     uint32_t    MinVddcPhases;
172     uint32_t    MinVddci;
173     uint32_t    MinMvdd;
175     uint32_t    MclkFrequency;
196     uint32_t    MpllFuncCntl;
197     uint32_t    MpllFuncCntl_1;
198     uint32_t    MpllFuncCntl_2;
199     uint32_t    MpllAdFuncCntl;
200     uint32_t    MpllDqFuncCntl;
201     uint32_t    MclkPwrmgtCntl;
202     uint32_t    DllCntl;
203     uint32_t    MpllSs1;
204     uint32_t    MpllSs2;
215     uint32_t    DownT;
216     uint32_t    UpT;
217     uint32_t    Reserved;
225     uint32_t McArbDramTiming;
226     uint32_t McArbDramTiming2;
242     uint32_t VclkFrequency;
243     uint32_t DclkFrequency;
255     uint32_t Frequency;
265     uint32_t SclkFrequency;
266     uint32_t MclkFrequency;
267     uint32_t VclkFrequency;
268     uint32_t DclkFrequency;
269     uint32_t SamclkFrequency;
270     uint32_t AclkFrequency;
271     uint32_t EclkFrequency;
294     uint32_t                            SystemFlags;
297     uint32_t                            SmioMaskVddcVid;
298     uint32_t                            SmioMaskVddcPhase;
299     uint32_t                            SmioMaskVddciVid;
300     uint32_t                            SmioMaskMvddVid;
302     uint32_t                            VddcLevelCount;
303     uint32_t                            VddciLevelCount;
304     uint32_t                            MvddLevelCount;
319     uint32_t                            Reserved[5];
333     uint32_t                            SclkStepSize;
334     uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
399     uint32_t                            BAPM_TEMP_GRADIENT;
401     uint32_t                            LowSclkInterruptT;
419     uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
450 	uint32_t RefreshPeriod;