Lines Matching refs:uint32_t

52     uint32_t    dpm2Flags;
65     uint32_t    SwitchDownCounter;
66     uint32_t    SysScalingFactor;
73     uint32_t    TDPLimit;
74     uint32_t    NearTDPLimit;
75     uint32_t    SafePowerLimit;
76     uint32_t    PowerBoostLimit;
77     uint32_t    MinLimitDelta;
83     uint32_t    EstimatedDGPU_T;
84     uint32_t    EstimatedDGPU_P;
85     uint32_t    EstimatedAPU_T;
86     uint32_t    EstimatedAPU_P;
94     uint32_t    NearTDPLimitTherm;
95     uint32_t    NearTDPLimitPAPM;
96     uint32_t    PlatformPowerLimit;
97     uint32_t    dGPU_T_Limit;
98     uint32_t    dGPU_T_Warning;
99     uint32_t    dGPU_T_Hysteresis;
105     uint32_t    vCG_SPLL_FUNC_CNTL;
106     uint32_t    vCG_SPLL_FUNC_CNTL_2;
107     uint32_t    vCG_SPLL_FUNC_CNTL_3;
108     uint32_t    vCG_SPLL_FUNC_CNTL_4;
109     uint32_t    vCG_SPLL_SPREAD_SPECTRUM;
110     uint32_t    vCG_SPLL_SPREAD_SPECTRUM_2;
111     uint32_t    sclk_value;
118     uint32_t    vMPLL_FUNC_CNTL;
119     uint32_t    vMPLL_FUNC_CNTL_1;
120     uint32_t    vMPLL_FUNC_CNTL_2;
121     uint32_t    vMPLL_AD_FUNC_CNTL;
122     uint32_t    vMPLL_DQ_FUNC_CNTL;
123     uint32_t    vMCLK_PWRMGT_CNTL;
124     uint32_t    vDLL_CNTL;
125     uint32_t    vMPLL_SS;
126     uint32_t    vMPLL_SS2;
127     uint32_t    mclk_value;
151     uint32_t                    aT;
152     uint32_t                    bSP;
163     uint32_t                    SQPowerThrottle;
164     uint32_t                    SQPowerThrottle_2;
165     uint32_t                    MaxPoweredUpCU;
168     uint32_t                    reserved[2];
201     uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
214     uint32_t                            lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
265 	uint32_t refresh_period;
282     uint32_t   lkge_lut_V0;
283     uint32_t   lkge_lut_Vstep;
284     uint32_t   WinTime;
285     uint32_t   R_LL;
286     uint32_t   calculation_repeats;
287     uint32_t   l2numWin_TDP;
288     uint32_t   dc_cac;
293     uint32_t   lkge_lut_T0;
294     uint32_t   lkge_lut_Tstep;
312     uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
329     uint32_t mc_arb_dram_timing;
330     uint32_t mc_arb_dram_timing2;
349     uint32_t    freq[256];
350     uint32_t    ss[256];
370     uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
371     uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
372     uint32_t K;
373     uint32_t T0;
374     uint32_t MaxT;
380     uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
381     uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
382     uint32_t Tthreshold;