Lines Matching refs:vddc
1772 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1777 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1786 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1789 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1791 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1810 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1813 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1819 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2291 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2348 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2357 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2547 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2548 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2549 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2550 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2944 u16 vddc, vddci; in si_apply_state_adjust_rules() local
2978 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
2979 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
2987 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
2988 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3037 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3040 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3046 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3057 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3063 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3064 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3094 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3100 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3103 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3108 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3109 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3115 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3174 u16 vddc, count = 0; in si_get_leakage_vddc() local
3178 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3180 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3181 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4105 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4108 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4120 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4123 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4130 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4359 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4360 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4366 &table->initialState.levels[0].vddc, in si_populate_smc_initial_state()
4370 table->initialState.levels[0].vddc.index, in si_populate_smc_initial_state()
4383 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4386 &table->initialState.levels[0].vddc); in si_populate_smc_initial_state()
4453 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4458 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4461 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4472 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4476 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4481 &table->ACPIState.levels[0].vddc, &std_vddc); in si_populate_smc_acpi_state()
4485 table->ACPIState.levels[0].vddc.index, in si_populate_smc_acpi_state()
4499 &table->ACPIState.levels[0].vddc); in si_populate_smc_acpi_state()
4590 state->levels[0].std_vddc = state->levels[0].vddc; in si_populate_ulv_state()
4697 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
4985 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
4990 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
4995 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5009 pl->vddc, in si_convert_power_level_to_smc()
5012 &level->vddc); in si_convert_power_level_to_smc()
5101 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5238 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5611 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6671 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6680 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6683 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6686 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6702 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6703 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6705 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6706 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6710 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
6711 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6714 pl->vddc = vddc; in si_parse_pplib_clock_info()
6723 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6999 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()