1868 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_powertune_defaults()  local
1872 		si_pi->cac_weights = cac_weights_tahiti;  in si_initialize_powertune_defaults()
1873 		si_pi->lcac_config = lcac_tahiti;  in si_initialize_powertune_defaults()
1874 		si_pi->cac_override = cac_override_tahiti;  in si_initialize_powertune_defaults()
1875 		si_pi->powertune_data = &powertune_data_tahiti;  in si_initialize_powertune_defaults()
1876 		si_pi->dte_data = dte_data_tahiti;  in si_initialize_powertune_defaults()
1880 			si_pi->dte_data.enable_dte_by_default = true;  in si_initialize_powertune_defaults()
1883 			si_pi->dte_data = dte_data_new_zealand;  in si_initialize_powertune_defaults()
1889 			si_pi->dte_data = dte_data_aruba_pro;  in si_initialize_powertune_defaults()
1893 			si_pi->dte_data = dte_data_malta;  in si_initialize_powertune_defaults()
1897 			si_pi->dte_data = dte_data_tahiti_pro;  in si_initialize_powertune_defaults()
1901 			if (si_pi->dte_data.enable_dte_by_default == true)  in si_initialize_powertune_defaults()
1909 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1910 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1911 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1912 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1913 			si_pi->dte_data = dte_data_curacao_xt;  in si_initialize_powertune_defaults()
1918 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1919 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1920 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1921 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1922 			si_pi->dte_data = dte_data_curacao_pro;  in si_initialize_powertune_defaults()
1927 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1928 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1929 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1930 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1931 			si_pi->dte_data = dte_data_neptune_xt;  in si_initialize_powertune_defaults()
1935 			si_pi->cac_weights = cac_weights_pitcairn;  in si_initialize_powertune_defaults()
1936 			si_pi->lcac_config = lcac_pitcairn;  in si_initialize_powertune_defaults()
1937 			si_pi->cac_override = cac_override_pitcairn;  in si_initialize_powertune_defaults()
1938 			si_pi->powertune_data = &powertune_data_pitcairn;  in si_initialize_powertune_defaults()
1939 			si_pi->dte_data = dte_data_pitcairn;  in si_initialize_powertune_defaults()
1943 		si_pi->lcac_config = lcac_cape_verde;  in si_initialize_powertune_defaults()
1944 		si_pi->cac_override = cac_override_cape_verde;  in si_initialize_powertune_defaults()
1945 		si_pi->powertune_data = &powertune_data_cape_verde;  in si_initialize_powertune_defaults()
1952 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1953 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1956 			si_pi->cac_weights = cac_weights_cape_verde_pro;  in si_initialize_powertune_defaults()
1957 			si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
1961 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1962 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1966 			si_pi->cac_weights = cac_weights_chelsea_xt;  in si_initialize_powertune_defaults()
1967 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1970 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1971 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1974 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1975 			si_pi->dte_data = dte_data_venus_xtx;  in si_initialize_powertune_defaults()
1978 			si_pi->cac_weights = cac_weights_heathrow;  in si_initialize_powertune_defaults()
1979 			si_pi->dte_data = dte_data_venus_xt;  in si_initialize_powertune_defaults()
1985 			si_pi->cac_weights = cac_weights_chelsea_pro;  in si_initialize_powertune_defaults()
1986 			si_pi->dte_data = dte_data_venus_pro;  in si_initialize_powertune_defaults()
1989 			si_pi->cac_weights = cac_weights_cape_verde;  in si_initialize_powertune_defaults()
1990 			si_pi->dte_data = dte_data_cape_verde;  in si_initialize_powertune_defaults()
1999 			si_pi->cac_weights = cac_weights_mars_pro;  in si_initialize_powertune_defaults()
2000 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2001 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2002 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2003 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2010 			si_pi->cac_weights = cac_weights_mars_xt;  in si_initialize_powertune_defaults()
2011 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2012 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2013 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2014 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2020 			si_pi->cac_weights = cac_weights_oland_pro;  in si_initialize_powertune_defaults()
2021 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2022 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2023 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2024 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2028 			si_pi->cac_weights = cac_weights_oland_xt;  in si_initialize_powertune_defaults()
2029 			si_pi->lcac_config = lcac_mars_pro;  in si_initialize_powertune_defaults()
2030 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2031 			si_pi->powertune_data = &powertune_data_mars_pro;  in si_initialize_powertune_defaults()
2032 			si_pi->dte_data = dte_data_mars_pro;  in si_initialize_powertune_defaults()
2036 			si_pi->cac_weights = cac_weights_oland;  in si_initialize_powertune_defaults()
2037 			si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2038 			si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2039 			si_pi->powertune_data = &powertune_data_oland;  in si_initialize_powertune_defaults()
2040 			si_pi->dte_data = dte_data_oland;  in si_initialize_powertune_defaults()
2044 		si_pi->cac_weights = cac_weights_hainan;  in si_initialize_powertune_defaults()
2045 		si_pi->lcac_config = lcac_oland;  in si_initialize_powertune_defaults()
2046 		si_pi->cac_override = cac_override_oland;  in si_initialize_powertune_defaults()
2047 		si_pi->powertune_data = &powertune_data_hainan;  in si_initialize_powertune_defaults()
2048 		si_pi->dte_data = dte_data_sun_xt;  in si_initialize_powertune_defaults()
2058 	si_pi->enable_dte = false;  in si_initialize_powertune_defaults()
2060 	if (si_pi->powertune_data->enable_powertune_by_default) {  in si_initialize_powertune_defaults()
2063 		if (si_pi->dte_data.enable_dte_by_default) {  in si_initialize_powertune_defaults()
2064 			si_pi->enable_dte = true;  in si_initialize_powertune_defaults()
2066 				si_update_dte_from_pl2(rdev, &si_pi->dte_data);  in si_initialize_powertune_defaults()
2077 		si_pi->dyn_powertune_data.l2_lta_window_size =  in si_initialize_powertune_defaults()
2078 			si_pi->powertune_data->l2_lta_window_size_default;  in si_initialize_powertune_defaults()
2079 		si_pi->dyn_powertune_data.lts_truncate =  in si_initialize_powertune_defaults()
2080 			si_pi->powertune_data->lts_truncate_default;  in si_initialize_powertune_defaults()
2083 		si_pi->dyn_powertune_data.l2_lta_window_size = 0;  in si_initialize_powertune_defaults()
2084 		si_pi->dyn_powertune_data.lts_truncate = 0;  in si_initialize_powertune_defaults()
2087 	si_pi->dyn_powertune_data.disable_uvd_powertune = false;  in si_initialize_powertune_defaults()
2157 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits()  local
2160 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits()
2189 					   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +  in si_populate_smc_tdp_limits()
2193 					   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2197 		if (si_pi->enable_ppm) {  in si_populate_smc_tdp_limits()
2198 			papm_parm = &si_pi->papm_parm;  in si_populate_smc_tdp_limits()
2207 			ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,  in si_populate_smc_tdp_limits()
2210 						   si_pi->sram_end);  in si_populate_smc_tdp_limits()
2222 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_tdp_limits_2()  local
2225 		SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;  in si_populate_smc_tdp_limits_2()
2237 					   (si_pi->state_table_start +  in si_populate_smc_tdp_limits_2()
2242 					   si_pi->sram_end);  in si_populate_smc_tdp_limits_2()
2275 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_should_disable_uvd_powertune()  local
2277 	if (si_pi->dyn_powertune_data.disable_uvd_powertune &&  in si_should_disable_uvd_powertune()
2467 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_dte_tables()  local
2469 	struct si_dte_data *dte_data = &si_pi->dte_data;  in si_initialize_smc_dte_tables()
2476 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2478 	if (si_pi->enable_dte == false)  in si_initialize_smc_dte_tables()
2486 		si_pi->enable_dte = false;  in si_initialize_smc_dte_tables()
2523 	ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,  in si_initialize_smc_dte_tables()
2524 				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);  in si_initialize_smc_dte_tables()
2533 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_cac_std_voltage_max_min()  local
2553 	if (si_pi->powertune_data->lkge_lut_v0_percent > 100)  in si_get_cac_std_voltage_max_min()
2556 	v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;  in si_get_cac_std_voltage_max_min()
2580 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_dte_leakage_table()  local
2597 							 &si_pi->powertune_data->leakage_coefficients,  in si_init_dte_leakage_table()
2600 							 si_pi->dyn_powertune_data.cac_leakage,  in si_init_dte_leakage_table()
2619 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_simplified_leakage_table()  local
2632 					   &si_pi->powertune_data->leakage_coefficients,  in si_init_simplified_leakage_table()
2633 					   si_pi->powertune_data->fixed_kt,  in si_init_simplified_leakage_table()
2635 					   si_pi->dyn_powertune_data.cac_leakage,  in si_init_simplified_leakage_table()
2653 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_smc_cac_tables()  local
2669 	reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);  in si_initialize_smc_cac_tables()
2672 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2673 	si_pi->dyn_powertune_data.dc_pwr_value =  in si_initialize_smc_cac_tables()
2674 		si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];  in si_initialize_smc_cac_tables()
2675 	si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);  in si_initialize_smc_cac_tables()
2676 	si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;  in si_initialize_smc_cac_tables()
2678 	si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;  in si_initialize_smc_cac_tables()
2689 	if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)  in si_initialize_smc_cac_tables()
2701 	cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);  in si_initialize_smc_cac_tables()
2702 	cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;  in si_initialize_smc_cac_tables()
2703 	cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;  in si_initialize_smc_cac_tables()
2707 	cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);  in si_initialize_smc_cac_tables()
2711 	cac_tables->cac_temp = si_pi->powertune_data->operating_temp;  in si_initialize_smc_cac_tables()
2715 	ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,  in si_initialize_smc_cac_tables()
2716 				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);  in si_initialize_smc_cac_tables()
2776 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_hardware_cac_manager()  local
2783 	ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);  in si_initialize_hardware_cac_manager()
2786 	ret = si_program_cac_config_registers(rdev, si_pi->cac_override);  in si_initialize_hardware_cac_manager()
2789 	ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);  in si_initialize_hardware_cac_manager()
2801 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_enable_smc_cac()  local
2822 				if (si_pi->enable_dte) {  in si_enable_smc_cac()
2829 			if (si_pi->enable_dte)  in si_enable_smc_cac()
2846 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_spll_table()  local
2856 	if (si_pi->spll_table_start == 0)  in si_init_smc_spll_table()
2902 		ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,  in si_init_smc_spll_table()
2904 					   si_pi->sram_end);  in si_init_smc_spll_table()
3125 	struct si_power_info *si_pi = si_get_pi(rdev);
3128 				      si_pi->soft_regs_start + reg_offset, value,
3129 				      si_pi->sram_end);
3136 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_write_smc_soft_register()  local
3139 				       si_pi->soft_regs_start + reg_offset,  in si_write_smc_soft_register()
3140 				       value, si_pi->sram_end);  in si_write_smc_soft_register()
3173 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_vddc()  local
3181 			si_pi->leakage_voltage.entries[count].voltage = vddc;  in si_get_leakage_vddc()
3182 			si_pi->leakage_voltage.entries[count].leakage_index =  in si_get_leakage_vddc()
3187 	si_pi->leakage_voltage.count = count;  in si_get_leakage_vddc()
3193 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_get_leakage_voltage_from_leakage_index()  local
3208 	for (i = 0; i < si_pi->leakage_voltage.count; i++) {  in si_get_leakage_voltage_from_leakage_index()
3209 		if (si_pi->leakage_voltage.entries[i].leakage_index == index) {  in si_get_leakage_voltage_from_leakage_index()
3210 			*leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;  in si_get_leakage_voltage_from_leakage_index()
3418 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_process_firmware_header()  local
3425 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3429         si_pi->state_table_start = tmp;  in si_process_firmware_header()
3434 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3438 	si_pi->soft_regs_start = tmp;  in si_process_firmware_header()
3443 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3447 	si_pi->mc_reg_table_start = tmp;  in si_process_firmware_header()
3452 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3456 	si_pi->fan_table_start = tmp;  in si_process_firmware_header()
3461 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3465 	si_pi->arb_table_start = tmp;  in si_process_firmware_header()
3470 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3474 	si_pi->cac_table_start = tmp;  in si_process_firmware_header()
3479 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3483 	si_pi->dte_table_start = tmp;  in si_process_firmware_header()
3488 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3492 	si_pi->spll_table_start = tmp;  in si_process_firmware_header()
3497 				     &tmp, si_pi->sram_end);  in si_process_firmware_header()
3501 	si_pi->papm_cfg_table_start = tmp;  in si_process_firmware_header()
3508 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_read_clock_registers()  local
3510 	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in si_read_clock_registers()
3511 	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3512 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in si_read_clock_registers()
3513 	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in si_read_clock_registers()
3514 	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in si_read_clock_registers()
3515 	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in si_read_clock_registers()
3516 	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in si_read_clock_registers()
3517 	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in si_read_clock_registers()
3518 	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in si_read_clock_registers()
3519 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in si_read_clock_registers()
3520 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in si_read_clock_registers()
3521 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in si_read_clock_registers()
3522 	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3523 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in si_read_clock_registers()
3524 	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in si_read_clock_registers()
3820 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_firmware()  local
3826 	ret = si_load_smc_ucode(rdev, si_pi->sram_end);  in si_upload_firmware()
3900 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_construct_voltage_tables()  local
3913 	} else if (si_pi->voltage_control_svi2) {  in si_construct_voltage_tables()
3934 	if (si_pi->vddci_control_svi2) {  in si_construct_voltage_tables()
3944 						    VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
3951 		if (si_pi->mvdd_voltage_table.count == 0) {  in si_construct_voltage_tables()
3956 		if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)  in si_construct_voltage_tables()
3959 								 &si_pi->mvdd_voltage_table);  in si_construct_voltage_tables()
3962 	if (si_pi->vddc_phase_shed_control) {  in si_construct_voltage_tables()
3964 						    VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);  in si_construct_voltage_tables()
3966 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
3968 		if ((si_pi->vddc_phase_shed_table.count == 0) ||  in si_construct_voltage_tables()
3969 		    (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))  in si_construct_voltage_tables()
3970 			si_pi->vddc_phase_shed_control = false;  in si_construct_voltage_tables()
3991 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_voltage_tables()  local
3994 	if (si_pi->voltage_control_svi2) {  in si_populate_smc_voltage_tables()
3996 			si_pi->svc_gpio_id);  in si_populate_smc_voltage_tables()
3998 			si_pi->svd_gpio_id);  in si_populate_smc_voltage_tables()
4023 		if (si_pi->mvdd_voltage_table.count) {  in si_populate_smc_voltage_tables()
4024 			si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);  in si_populate_smc_voltage_tables()
4027 				cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);  in si_populate_smc_voltage_tables()
4030 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_voltage_tables()
4031 			if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,  in si_populate_smc_voltage_tables()
4033 				si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);  in si_populate_smc_voltage_tables()
4036 					cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);  in si_populate_smc_voltage_tables()
4039 							   (u32)si_pi->vddc_phase_shed_table.phase_delay);  in si_populate_smc_voltage_tables()
4041 				si_pi->vddc_phase_shed_control = false;  in si_populate_smc_voltage_tables()
4073 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mvdd_value()  local
4079 			voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;  in si_populate_mvdd_value()
4081 		voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);  in si_populate_mvdd_value()
4168 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_arb_table_index()  local
4172 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);  in si_init_arb_table_index()
4179 	return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);  in si_init_arb_table_index()
4195 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_force_switch_to_arb_f0()  local
4199 	ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,  in si_force_switch_to_arb_f0()
4200 				     &tmp, si_pi->sram_end);  in si_force_switch_to_arb_f0()
4261 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_do_program_memory_timing_parameters()  local
4271 					   si_pi->arb_table_start +  in si_do_program_memory_timing_parameters()
4276 					   si_pi->sram_end);  in si_do_program_memory_timing_parameters()
4295 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_initial_mvdd_value()  local
4298 		return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,  in si_populate_initial_mvdd_value()
4299 						 si_pi->mvdd_bootup_value, voltage);  in si_populate_initial_mvdd_value()
4311 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_initial_state()  local
4316 		cpu_to_be32(si_pi->clock_registers.dll_cntl);  in si_populate_smc_initial_state()
4318 		cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);  in si_populate_smc_initial_state()
4320 		cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);  in si_populate_smc_initial_state()
4322 		cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);  in si_populate_smc_initial_state()
4324 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);  in si_populate_smc_initial_state()
4326 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);  in si_populate_smc_initial_state()
4328 		cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);  in si_populate_smc_initial_state()
4330 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_initial_state()
4332 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_initial_state()
4338 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);  in si_populate_smc_initial_state()
4340 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);  in si_populate_smc_initial_state()
4342 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);  in si_populate_smc_initial_state()
4344 		cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);  in si_populate_smc_initial_state()
4346 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);  in si_populate_smc_initial_state()
4348 		cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);  in si_populate_smc_initial_state()
4380 	if (si_pi->vddc_phase_shed_control)  in si_populate_smc_initial_state()
4395 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;  in si_populate_smc_initial_state()
4432 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_smc_acpi_state()  local
4433 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_populate_smc_acpi_state()
4434 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_populate_smc_acpi_state()
4435 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_populate_smc_acpi_state()
4436 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_populate_smc_acpi_state()
4437 	u32 dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_smc_acpi_state()
4438 	u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_smc_acpi_state()
4439 	u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_smc_acpi_state()
4440 	u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_smc_acpi_state()
4441 	u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_smc_acpi_state()
4442 	u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_smc_acpi_state()
4443 	u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_smc_acpi_state()
4464 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;  in si_populate_smc_acpi_state()
4466 		if (si_pi->vddc_phase_shed_control) {  in si_populate_smc_acpi_state()
4489 										    si_pi->sys_pcie_mask,  in si_populate_smc_acpi_state()
4490 										    si_pi->boot_pcie_gen,  in si_populate_smc_acpi_state()
4493 		if (si_pi->vddc_phase_shed_control)  in si_populate_smc_acpi_state()
4532 		cpu_to_be32(si_pi->clock_registers.mpll_ss1);  in si_populate_smc_acpi_state()
4534 		cpu_to_be32(si_pi->clock_registers.mpll_ss2);  in si_populate_smc_acpi_state()
4572 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_ulv_state()  local
4573 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()
4601 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_program_ulv_memory_timing_parameters()  local
4602 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()
4615 				   si_pi->arb_table_start +  in si_program_ulv_memory_timing_parameters()
4620 				   si_pi->sram_end);  in si_program_ulv_memory_timing_parameters()
4635 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_init_smc_table()  local
4637 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()
4638 	SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;  in si_init_smc_table()
4715 	return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,  in si_init_smc_table()
4717 				    si_pi->sram_end);  in si_init_smc_table()
4725 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_calculate_sclk_params()  local
4727 	u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;  in si_calculate_sclk_params()
4728 	u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;  in si_calculate_sclk_params()
4729 	u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;  in si_calculate_sclk_params()
4730 	u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;  in si_calculate_sclk_params()
4731 	u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;  in si_calculate_sclk_params()
4732 	u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;  in si_calculate_sclk_params()
4819 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mclk_value()  local
4820 	u32  dll_cntl = si_pi->clock_registers.dll_cntl;  in si_populate_mclk_value()
4821 	u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;  in si_populate_mclk_value()
4822 	u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;  in si_populate_mclk_value()
4823 	u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;  in si_populate_mclk_value()
4824 	u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;  in si_populate_mclk_value()
4825 	u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;  in si_populate_mclk_value()
4826 	u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;  in si_populate_mclk_value()
4827 	u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;  in si_populate_mclk_value()
4828 	u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;  in si_populate_mclk_value()
4921 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_level_to_smc()  local
4928 	    (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))  in si_convert_power_level_to_smc()
4929 		level->gen2PCIE = (u8)si_pi->force_pcie_gen;  in si_convert_power_level_to_smc()
5006 	if (si_pi->vddc_phase_shed_control) {  in si_convert_power_level_to_smc()
5017 	level->MaxPoweredUpCU = si_pi->max_cu;  in si_convert_power_level_to_smc()
5075 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_disable_ulv()  local
5076 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()
5088 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_is_state_ulv_compatible()  local
5089 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()
5116 	const struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_power_state_conditionally_enable_ulv()  local
5117 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()
5133 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_power_state_to_smc()  local
5158 			if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {  in si_convert_power_state_to_smc()
5210 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_sw_state()  local
5213 	u32 address = si_pi->state_table_start +  in si_upload_sw_state()
5218 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()
5227 				   state_size, si_pi->sram_end);  in si_upload_sw_state()
5234 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_ulv_state()  local
5235 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()
5239 		u32 address = si_pi->state_table_start +  in si_upload_ulv_state()
5241 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()
5249 						   state_size, si_pi->sram_end);  in si_upload_ulv_state()
5473 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_initialize_mc_reg_table()  local
5475 	struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;  in si_initialize_mc_reg_table()
5524 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_addresses()  local
5527 	for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {  in si_populate_mc_reg_addresses()
5528 		if (si_pi->mc_reg_table.valid_flag & (1 << j)) {  in si_populate_mc_reg_addresses()
5532 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);  in si_populate_mc_reg_addresses()
5534 				cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);  in si_populate_mc_reg_addresses()
5559 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_convert_mc_reg_table_entry_to_smc()  local
5562 	for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {  in si_convert_mc_reg_table_entry_to_smc()
5563 		if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in si_convert_mc_reg_table_entry_to_smc()
5567 	if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))  in si_convert_mc_reg_table_entry_to_smc()
5570 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],  in si_convert_mc_reg_table_entry_to_smc()
5571 				mc_reg_table_data, si_pi->mc_reg_table.last,  in si_convert_mc_reg_table_entry_to_smc()
5572 				si_pi->mc_reg_table.valid_flag);  in si_convert_mc_reg_table_entry_to_smc()
5593 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_populate_mc_reg_table()  local
5594 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()
5595 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_populate_mc_reg_table()
5606 	si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5608 				si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5609 				si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5615 		si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],  in si_populate_mc_reg_table()
5617 					si_pi->mc_reg_table.last,  in si_populate_mc_reg_table()
5618 					si_pi->mc_reg_table.valid_flag);  in si_populate_mc_reg_table()
5622 	return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,  in si_populate_mc_reg_table()
5624 				    sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);  in si_populate_mc_reg_table()
5631 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_upload_mc_reg_table()  local
5632 	u32 address = si_pi->mc_reg_table_start +  in si_upload_mc_reg_table()
5635 	SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;  in si_upload_mc_reg_table()
5645 				    si_pi->sram_end);  in si_upload_mc_reg_table()
5686 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_request_link_speed_change_before_state_change()  local
5690 	if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)  in si_request_link_speed_change_before_state_change()
5693 		current_link_speed = si_pi->force_pcie_gen;  in si_request_link_speed_change_before_state_change()
5695 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_request_link_speed_change_before_state_change()
5696 	si_pi->pspp_notify_required = false;  in si_request_link_speed_change_before_state_change()
5703 			si_pi->force_pcie_gen = RADEON_PCIE_GEN2;  in si_request_link_speed_change_before_state_change()
5711 			si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);  in si_request_link_speed_change_before_state_change()
5716 			si_pi->pspp_notify_required = true;  in si_request_link_speed_change_before_state_change()
5724 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_notify_link_speed_change_after_state_change()  local
5728 	if (si_pi->pspp_notify_required) {  in si_notify_link_speed_change_after_state_change()
5767 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_set_max_cu_value()  local
5776 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5782 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5790 			si_pi->max_cu = 10;  in si_set_max_cu_value()
5795 			si_pi->max_cu = 8;  in si_set_max_cu_value()
5798 			si_pi->max_cu = 0;  in si_set_max_cu_value()
5802 		si_pi->max_cu = 0;  in si_set_max_cu_value()
5931 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_static_mode()  local
5934 	if (si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_static_mode()
5936 		si_pi->fan_ctrl_default_mode = tmp;  in si_fan_ctrl_set_static_mode()
5938 		si_pi->t_min = tmp;  in si_fan_ctrl_set_static_mode()
5939 		si_pi->fan_ctrl_is_in_default_mode = false;  in si_fan_ctrl_set_static_mode()
5953 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_thermal_setup_fan_table()  local
5962 	if (!si_pi->fan_table_start) {  in si_thermal_setup_fan_table()
6015 				   si_pi->fan_table_start,  in si_thermal_setup_fan_table()
6018 				   si_pi->sram_end);  in si_thermal_setup_fan_table()
6030 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_start_smc_fan_control()  local
6035 		si_pi->fan_is_controlled_by_smc = true;  in si_fan_ctrl_start_smc_fan_control()
6044 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_stop_smc_fan_control()  local
6050 		si_pi->fan_is_controlled_by_smc = false;  in si_fan_ctrl_stop_smc_fan_control()
6085 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_fan_speed_percent()  local
6093 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_set_fan_speed_percent()
6133 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_get_mode()  local
6136 	if (si_pi->fan_is_controlled_by_smc)  in si_fan_ctrl_get_mode()
6197 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_fan_ctrl_set_default_mode()  local
6200 	if (!si_pi->fan_ctrl_is_in_default_mode) {  in si_fan_ctrl_set_default_mode()
6202 		tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);  in si_fan_ctrl_set_default_mode()
6206 		tmp |= TMIN(si_pi->t_min);  in si_fan_ctrl_set_default_mode()
6208 		si_pi->fan_ctrl_is_in_default_mode = true;  in si_fan_ctrl_set_default_mode()
6274 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_dpm_enable()  local
6280 	if (pi->voltage_control || si_pi->voltage_control_svi2)  in si_dpm_enable()
6284 	if (pi->voltage_control || si_pi->voltage_control_svi2) {  in si_dpm_enable()
6658 	struct si_power_info *si_pi = si_get_pi(rdev);  in si_parse_pplib_clock_info()  local
6675 						 si_pi->sys_pcie_mask,  in si_parse_pplib_clock_info()
6676 						 si_pi->boot_pcie_gen,  in si_parse_pplib_clock_info()
6688 		si_pi->acpi_pcie_gen = pl->pcie_gen;  in si_parse_pplib_clock_info()
6694 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
6695 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6696 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
6697 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
6698 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
6699 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()
6716 		si_pi->mvdd_bootup_value = mvdd;  in si_parse_pplib_clock_info()
6809 	struct si_power_info *si_pi;  in si_dpm_init()  local
6814 	si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);  in si_dpm_init()
6815 	if (si_pi == NULL)  in si_dpm_init()
6817 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6818 	ni_pi = &si_pi->ni;  in si_dpm_init()
6824 		si_pi->sys_pcie_mask = 0;  in si_dpm_init()
6826 		si_pi->sys_pcie_mask = mask;  in si_dpm_init()
6827 	si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;  in si_dpm_init()
6828 	si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);  in si_dpm_init()
6896 		si_pi->voltage_control_svi2 =  in si_dpm_init()
6899 		if (si_pi->voltage_control_svi2)  in si_dpm_init()
6901 						  &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);  in si_dpm_init()
6912 		si_pi->vddci_control_svi2 =  in si_dpm_init()
6916 	si_pi->vddc_phase_shed_control =  in si_dpm_init()
6929 	si_pi->sclk_deep_sleep_above_low = false;  in si_dpm_init()
6946 	si_pi->sram_end = SMC_RAM_END;  in si_dpm_init()
6964 	si_pi->fan_ctrl_is_in_default_mode = true;  in si_dpm_init()