Lines Matching refs:rdev
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1744 static int si_populate_voltage_value(struct radeon_device *rdev,
1747 static int si_get_std_voltage_value(struct radeon_device *rdev,
1750 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1755 static int si_calculate_sclk_params(struct radeon_device *rdev,
1759 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1760 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762 static struct si_power_info *si_get_pi(struct radeon_device *rdev) in si_get_pi() argument
1764 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, in si_calculate_leakage_for_v_and_t() argument
1824 static void si_calculate_leakage_for_v(struct radeon_device *rdev, in si_calculate_leakage_for_v() argument
1835 static void si_update_dte_from_pl2(struct radeon_device *rdev, in si_update_dte_from_pl2() argument
1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1865 static void si_initialize_powertune_defaults(struct radeon_device *rdev) in si_initialize_powertune_defaults() argument
1867 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_powertune_defaults()
1868 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_powertune_defaults()
1871 if (rdev->family == CHIP_TAHITI) { in si_initialize_powertune_defaults()
1878 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1905 } else if (rdev->family == CHIP_PITCAIRN) { in si_initialize_powertune_defaults()
1906 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1942 } else if (rdev->family == CHIP_VERDE) { in si_initialize_powertune_defaults()
1947 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1993 } else if (rdev->family == CHIP_OLAND) { in si_initialize_powertune_defaults()
1994 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
2043 } else if (rdev->family == CHIP_HAINAN) { in si_initialize_powertune_defaults()
2066 si_update_dte_from_pl2(rdev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2090 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) in si_get_smc_power_scaling_factor() argument
2095 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) in si_calculate_cac_wintime() argument
2102 xclk = radeon_get_xclk(rdev); in si_calculate_cac_wintime()
2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, in si_calculate_adjusted_tdp_limits() argument
2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2153 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, in si_populate_smc_tdp_limits() argument
2156 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits()
2157 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits()
2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2163 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits()
2173 ret = si_calculate_adjusted_tdp_limits(rdev, in si_populate_smc_tdp_limits()
2175 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2188 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits()
2207 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2218 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, in si_populate_smc_tdp_limits_2() argument
2221 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2222 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2226 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits_2()
2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2234 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2236 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits_2()
2250 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, in si_calculate_power_efficiency_ratio() argument
2272 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, in si_should_disable_uvd_powertune() argument
2275 struct si_power_info *si_pi = si_get_pi(rdev); in si_should_disable_uvd_powertune()
2284 static int si_populate_power_containment_values(struct radeon_device *rdev, in si_populate_power_containment_values() argument
2288 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_power_containment_values()
2289 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_power_containment_values()
2312 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); in si_populate_power_containment_values()
2347 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2356 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2365 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, in si_populate_power_containment_values()
2378 static int si_populate_sq_ramping_values(struct radeon_device *rdev, in si_populate_sq_ramping_values() argument
2382 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_sq_ramping_values()
2394 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2435 static int si_enable_power_containment(struct radeon_device *rdev, in si_enable_power_containment() argument
2439 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_power_containment()
2445 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_power_containment()
2446 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); in si_enable_power_containment()
2455 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); in si_enable_power_containment()
2465 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) in si_initialize_smc_dte_tables() argument
2467 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_dte_tables()
2523 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, in si_initialize_smc_dte_tables()
2530 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, in si_get_cac_std_voltage_max_min() argument
2533 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_cac_std_voltage_max_min()
2535 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2575 static int si_init_dte_leakage_table(struct radeon_device *rdev, in si_init_dte_leakage_table() argument
2580 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_dte_leakage_table()
2588 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_dte_leakage_table()
2596 si_calculate_leakage_for_v_and_t(rdev, in si_init_dte_leakage_table()
2615 static int si_init_simplified_leakage_table(struct radeon_device *rdev, in si_init_simplified_leakage_table() argument
2619 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_simplified_leakage_table()
2626 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_simplified_leakage_table()
2631 si_calculate_leakage_for_v(rdev, in si_init_simplified_leakage_table()
2650 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) in si_initialize_smc_cac_tables() argument
2652 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_smc_cac_tables()
2653 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_cac_tables()
2659 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; in si_initialize_smc_cac_tables()
2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2675 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); in si_initialize_smc_cac_tables()
2680 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); in si_initialize_smc_cac_tables()
2690 ret = si_init_dte_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2694 ret = si_init_simplified_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2715 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, in si_initialize_smc_cac_tables()
2721 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); in si_initialize_smc_cac_tables()
2734 static int si_program_cac_config_registers(struct radeon_device *rdev, in si_program_cac_config_registers() argument
2773 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) in si_initialize_hardware_cac_manager() argument
2775 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_hardware_cac_manager()
2776 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_hardware_cac_manager()
2783 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2796 static int si_enable_smc_cac(struct radeon_device *rdev, in si_enable_smc_cac() argument
2800 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_smc_cac()
2801 struct si_power_info *si_pi = si_get_pi(rdev); in si_enable_smc_cac()
2807 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_smc_cac()
2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); in si_enable_smc_cac()
2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); in si_enable_smc_cac()
2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); in si_enable_smc_cac()
2830 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); in si_enable_smc_cac()
2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); in si_enable_smc_cac()
2837 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); in si_enable_smc_cac()
2843 static int si_init_smc_spll_table(struct radeon_device *rdev) in si_init_smc_spll_table() argument
2845 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_init_smc_spll_table()
2846 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_spll_table()
2864 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2902 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, in si_init_smc_spll_table()
2936 static void si_apply_state_adjust_rules(struct radeon_device *rdev, in si_apply_state_adjust_rules() argument
2952 if (rdev->pdev->vendor == p->chip_vendor && in si_apply_state_adjust_rules()
2953 rdev->pdev->device == p->chip_device && in si_apply_state_adjust_rules()
2954 rdev->pdev->subsystem_vendor == p->subsys_vendor && in si_apply_state_adjust_rules()
2955 rdev->pdev->subsystem_device == p->subsys_device) { in si_apply_state_adjust_rules()
2963 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
2964 ni_dpm_vblank_too_short(rdev)) in si_apply_state_adjust_rules()
2972 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
2973 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
2975 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
2981 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
2995 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
2997 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
2999 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3088 btc_adjust_clock_combinations(rdev, max_limits, in si_apply_state_adjust_rules()
3092 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3095 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3098 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3101 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3102 rdev->clock.current_dispclk, in si_apply_state_adjust_rules()
3107 btc_apply_voltage_delta_rules(rdev, in si_apply_state_adjust_rules()
3115 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3122 static int si_read_smc_soft_register(struct radeon_device *rdev,
3125 struct si_power_info *si_pi = si_get_pi(rdev);
3127 return si_read_smc_sram_dword(rdev,
3133 static int si_write_smc_soft_register(struct radeon_device *rdev, in si_write_smc_soft_register() argument
3136 struct si_power_info *si_pi = si_get_pi(rdev); in si_write_smc_soft_register()
3138 return si_write_smc_sram_dword(rdev, in si_write_smc_soft_register()
3143 static bool si_is_special_1gb_platform(struct radeon_device *rdev) in si_is_special_1gb_platform() argument
3164 if ((rdev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3171 static void si_get_leakage_vddc(struct radeon_device *rdev) in si_get_leakage_vddc() argument
3173 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_vddc()
3178 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3190 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, in si_get_leakage_voltage_from_leakage_index() argument
3193 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_voltage_from_leakage_index()
3217 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in si_set_dpm_event_sources() argument
3219 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_dpm_event_sources()
3252 static void si_enable_auto_throttle_source(struct radeon_device *rdev, in si_enable_auto_throttle_source() argument
3256 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_auto_throttle_source()
3261 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3266 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3271 static void si_start_dpm(struct radeon_device *rdev) in si_start_dpm() argument
3276 static void si_stop_dpm(struct radeon_device *rdev) in si_stop_dpm() argument
3281 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) in si_enable_sclk_control() argument
3291 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3297 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3306 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3308 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3313 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3316 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3323 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, in si_send_msg_to_smc_with_parameter() argument
3327 return si_send_msg_to_smc(rdev, msg); in si_send_msg_to_smc_with_parameter()
3330 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) in si_restrict_performance_levels_before_switch() argument
3332 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) in si_restrict_performance_levels_before_switch()
3335 …return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK)… in si_restrict_performance_levels_before_switch()
3339 int si_dpm_force_performance_level(struct radeon_device *rdev, in si_dpm_force_performance_level() argument
3342 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3347 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3350 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3353 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3356 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3359 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3362 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3366 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3372 static int si_set_boot_state(struct radeon_device *rdev)
3374 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3379 static int si_set_sw_state(struct radeon_device *rdev) in si_set_sw_state() argument
3381 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? in si_set_sw_state()
3385 static int si_halt_smc(struct radeon_device *rdev) in si_halt_smc() argument
3387 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) in si_halt_smc()
3390 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? in si_halt_smc()
3394 static int si_resume_smc(struct radeon_device *rdev) in si_resume_smc() argument
3396 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) in si_resume_smc()
3399 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? in si_resume_smc()
3403 static void si_dpm_start_smc(struct radeon_device *rdev) in si_dpm_start_smc() argument
3405 si_program_jump_on_start(rdev); in si_dpm_start_smc()
3406 si_start_smc(rdev); in si_dpm_start_smc()
3407 si_start_smc_clock(rdev); in si_dpm_start_smc()
3410 static void si_dpm_stop_smc(struct radeon_device *rdev) in si_dpm_stop_smc() argument
3412 si_reset_smc(rdev); in si_dpm_stop_smc()
3413 si_stop_smc_clock(rdev); in si_dpm_stop_smc()
3416 static int si_process_firmware_header(struct radeon_device *rdev) in si_process_firmware_header() argument
3418 struct si_power_info *si_pi = si_get_pi(rdev); in si_process_firmware_header()
3422 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3431 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3440 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3449 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3458 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3467 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3476 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3485 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3494 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3506 static void si_read_clock_registers(struct radeon_device *rdev) in si_read_clock_registers() argument
3508 struct si_power_info *si_pi = si_get_pi(rdev); in si_read_clock_registers()
3527 static void si_enable_thermal_protection(struct radeon_device *rdev, in si_enable_thermal_protection() argument
3536 static void si_enable_acpi_power_management(struct radeon_device *rdev) in si_enable_acpi_power_management() argument
3542 static int si_enter_ulp_state(struct radeon_device *rdev)
3551 static int si_exit_ulp_state(struct radeon_device *rdev)
3559 for (i = 0; i < rdev->usec_timeout; i++) {
3569 static int si_notify_smc_display_change(struct radeon_device *rdev, in si_notify_smc_display_change() argument
3575 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? in si_notify_smc_display_change()
3579 static void si_program_response_times(struct radeon_device *rdev) in si_program_response_times() argument
3585 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); in si_program_response_times()
3587 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3588 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; in si_program_response_times()
3596 reference_clock = radeon_get_xclk(rdev); in si_program_response_times()
3602 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); in si_program_response_times()
3603 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); in si_program_response_times()
3604 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); in si_program_response_times()
3605 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); in si_program_response_times()
3608 static void si_program_ds_registers(struct radeon_device *rdev) in si_program_ds_registers() argument
3610 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_program_ds_registers()
3620 static void si_program_display_gap(struct radeon_device *rdev) in si_program_display_gap() argument
3626 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3631 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3641 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3642 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3644 for (i = 0; i < rdev->num_crtc; i++) { in si_program_display_gap()
3645 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3648 if (i == rdev->num_crtc) in si_program_display_gap()
3662 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3665 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) in si_enable_spread_spectrum() argument
3667 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_spread_spectrum()
3678 static void si_setup_bsp(struct radeon_device *rdev) in si_setup_bsp() argument
3680 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_setup_bsp()
3681 u32 xclk = radeon_get_xclk(rdev); in si_setup_bsp()
3702 static void si_program_git(struct radeon_device *rdev) in si_program_git() argument
3707 static void si_program_tp(struct radeon_device *rdev) in si_program_tp() argument
3727 static void si_program_tpp(struct radeon_device *rdev) in si_program_tpp() argument
3732 static void si_program_sstp(struct radeon_device *rdev) in si_program_sstp() argument
3737 static void si_enable_display_gap(struct radeon_device *rdev) in si_enable_display_gap() argument
3751 static void si_program_vc(struct radeon_device *rdev) in si_program_vc() argument
3753 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_program_vc()
3758 static void si_clear_vc(struct radeon_device *rdev) in si_clear_vc() argument
3798 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3800 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_strobe_mode_settings()
3818 static int si_upload_firmware(struct radeon_device *rdev) in si_upload_firmware() argument
3820 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_firmware()
3823 si_reset_smc(rdev); in si_upload_firmware()
3824 si_stop_smc_clock(rdev); in si_upload_firmware()
3826 ret = si_load_smc_ucode(rdev, si_pi->sram_end); in si_upload_firmware()
3831 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, in si_validate_phase_shedding_tables() argument
3858 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, in si_trim_voltage_table_to_fit_state_table() argument
3875 static int si_get_svi2_voltage_table(struct radeon_device *rdev, in si_get_svi2_voltage_table() argument
3896 static int si_construct_voltage_tables(struct radeon_device *rdev) in si_construct_voltage_tables() argument
3898 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_construct_voltage_tables()
3899 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_construct_voltage_tables()
3900 struct si_power_info *si_pi = si_get_pi(rdev); in si_construct_voltage_tables()
3904 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
3910 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3914 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
3915 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3924 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, in si_construct_voltage_tables()
3930 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3935 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
3936 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
3943 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, in si_construct_voltage_tables()
3957 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3963 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
3976 static void si_populate_smc_voltage_table(struct radeon_device *rdev, in si_populate_smc_voltage_table() argument
3986 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, in si_populate_smc_voltage_tables() argument
3989 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_voltage_tables()
3990 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_voltage_tables()
3991 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_voltage_tables()
3995 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, in si_populate_smc_voltage_tables()
3997 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, in si_populate_smc_voltage_tables()
3999 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, in si_populate_smc_voltage_tables()
4003 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); in si_populate_smc_voltage_tables()
4016 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); in si_populate_smc_voltage_tables()
4024 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4031 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4032 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4033 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4038 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, in si_populate_smc_voltage_tables()
4049 static int si_populate_voltage_value(struct radeon_device *rdev, in si_populate_voltage_value() argument
4069 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4072 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mvdd_value()
4073 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mvdd_value()
4086 static int si_get_std_voltage_value(struct radeon_device *rdev, in si_get_std_voltage_value() argument
4094 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4095 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4096 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4099 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4101 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4103 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4105 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4108 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4114 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4116 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4118 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4120 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4123 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4129 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4130 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4137 static int si_populate_std_voltage_value(struct radeon_device *rdev, in si_populate_std_voltage_value() argument
4147 static int si_populate_phase_shedding_value(struct radeon_device *rdev, in si_populate_phase_shedding_value() argument
4166 static int si_init_arb_table_index(struct radeon_device *rdev) in si_init_arb_table_index() argument
4168 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_arb_table_index()
4172 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); in si_init_arb_table_index()
4179 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); in si_init_arb_table_index()
4182 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) in si_initial_switch_from_arb_f0_to_f1() argument
4184 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); in si_initial_switch_from_arb_f0_to_f1()
4187 static int si_reset_to_default(struct radeon_device *rdev) in si_reset_to_default() argument
4189 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? in si_reset_to_default()
4193 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) in si_force_switch_to_arb_f0() argument
4195 struct si_power_info *si_pi = si_get_pi(rdev); in si_force_switch_to_arb_f0()
4199 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4209 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); in si_force_switch_to_arb_f0()
4212 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, in si_calculate_memory_refresh_rate() argument
4231 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, in si_populate_memory_timing_parameters() argument
4240 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); in si_populate_memory_timing_parameters()
4242 radeon_atom_set_engine_dram_timings(rdev, in si_populate_memory_timing_parameters()
4257 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, in si_do_program_memory_timing_parameters() argument
4261 struct si_power_info *si_pi = si_get_pi(rdev); in si_do_program_memory_timing_parameters()
4267 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4270 ret = si_copy_bytes_to_smc(rdev, in si_do_program_memory_timing_parameters()
4284 static int si_program_memory_timing_parameters(struct radeon_device *rdev, in si_program_memory_timing_parameters() argument
4287 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, in si_program_memory_timing_parameters()
4291 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, in si_populate_initial_mvdd_value() argument
4294 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_initial_mvdd_value()
4295 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_initial_mvdd_value()
4298 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4304 static int si_populate_smc_initial_state(struct radeon_device *rdev, in si_populate_smc_initial_state() argument
4309 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_initial_state()
4310 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_initial_state()
4311 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_initial_state()
4358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_initial_state()
4365 ret = si_get_std_voltage_value(rdev, in si_populate_smc_initial_state()
4369 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_initial_state()
4375 si_populate_voltage_value(rdev, in si_populate_smc_initial_state()
4381 si_populate_phase_shedding_value(rdev, in si_populate_smc_initial_state()
4382 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4388 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); in si_populate_smc_initial_state()
4399 si_get_strobe_mode_settings(rdev, in si_populate_smc_initial_state()
4427 static int si_populate_smc_acpi_state(struct radeon_device *rdev, in si_populate_smc_acpi_state() argument
4430 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_acpi_state()
4431 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_acpi_state()
4432 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_acpi_state()
4452 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4457 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4460 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4467 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4468 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4475 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4480 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4484 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4488 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, in si_populate_smc_acpi_state()
4494 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4495 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4504 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_populate_smc_acpi_state()
4548 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); in si_populate_smc_acpi_state()
4568 static int si_populate_ulv_state(struct radeon_device *rdev, in si_populate_ulv_state() argument
4571 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_ulv_state()
4572 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_ulv_state()
4577 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, in si_populate_ulv_state()
4599 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) in si_program_ulv_memory_timing_parameters() argument
4601 struct si_power_info *si_pi = si_get_pi(rdev); in si_program_ulv_memory_timing_parameters()
4606 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
4611 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, in si_program_ulv_memory_timing_parameters()
4614 ret = si_copy_bytes_to_smc(rdev, in si_program_ulv_memory_timing_parameters()
4625 static void si_get_mvdd_configuration(struct radeon_device *rdev) in si_get_mvdd_configuration() argument
4627 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_mvdd_configuration()
4632 static int si_init_smc_table(struct radeon_device *rdev) in si_init_smc_table() argument
4634 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_init_smc_table()
4635 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_table()
4636 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4643 si_populate_smc_voltage_tables(rdev, table); in si_init_smc_table()
4645 switch (rdev->pm.int_thermal_type) { in si_init_smc_table()
4658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4661 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4662 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) in si_init_smc_table()
4666 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4672 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4675 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4677 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
4678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, in si_init_smc_table()
4682 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); in si_init_smc_table()
4686 ret = si_populate_smc_acpi_state(rdev, table); in si_init_smc_table()
4692 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, in si_init_smc_table()
4698 ret = si_populate_ulv_state(rdev, &table->ULVState); in si_init_smc_table()
4702 ret = si_program_ulv_memory_timing_parameters(rdev); in si_init_smc_table()
4709 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4710 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
4715 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, in si_init_smc_table()
4720 static int si_calculate_sclk_params(struct radeon_device *rdev, in si_calculate_sclk_params() argument
4724 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_calculate_sclk_params()
4725 struct si_power_info *si_pi = si_get_pi(rdev); in si_calculate_sclk_params()
4734 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
4739 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_calculate_sclk_params()
4765 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_calculate_sclk_params()
4790 static int si_populate_sclk_value(struct radeon_device *rdev, in si_populate_sclk_value() argument
4797 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
4811 static int si_populate_mclk_value(struct radeon_device *rdev, in si_populate_mclk_value() argument
4818 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mclk_value()
4819 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mclk_value()
4832 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in si_populate_mclk_value()
4856 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
4865 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_populate_mclk_value()
4900 static void si_populate_smc_sp(struct radeon_device *rdev, in si_populate_smc_sp() argument
4905 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_sp()
4915 static int si_convert_power_level_to_smc(struct radeon_device *rdev, in si_convert_power_level_to_smc() argument
4919 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_convert_power_level_to_smc()
4920 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_level_to_smc()
4921 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_level_to_smc()
4933 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
4943 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
4957 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
4969 level->strobeMode = si_get_strobe_mode_settings(rdev, in si_convert_power_level_to_smc()
4975 ret = si_populate_mclk_value(rdev, in si_convert_power_level_to_smc()
4983 ret = si_populate_voltage_value(rdev, in si_convert_power_level_to_smc()
4990 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
4994 ret = si_populate_std_voltage_value(rdev, std_vddc, in si_convert_power_level_to_smc()
5000 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_convert_power_level_to_smc()
5007 ret = si_populate_phase_shedding_value(rdev, in si_convert_power_level_to_smc()
5008 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5019 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5024 static int si_populate_smc_t(struct radeon_device *rdev, in si_populate_smc_t() argument
5028 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_t()
5073 static int si_disable_ulv(struct radeon_device *rdev) in si_disable_ulv() argument
5075 struct si_power_info *si_pi = si_get_pi(rdev); in si_disable_ulv()
5079 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? in si_disable_ulv()
5085 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, in si_is_state_ulv_compatible() argument
5088 const struct si_power_info *si_pi = si_get_pi(rdev); in si_is_state_ulv_compatible()
5098 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5099 if (rdev->clock.current_dispclk <= in si_is_state_ulv_compatible()
5100 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5102 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5113 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, in si_set_power_state_conditionally_enable_ulv() argument
5116 const struct si_power_info *si_pi = si_get_pi(rdev); in si_set_power_state_conditionally_enable_ulv()
5120 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) in si_set_power_state_conditionally_enable_ulv()
5121 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? in si_set_power_state_conditionally_enable_ulv()
5127 static int si_convert_power_state_to_smc(struct radeon_device *rdev, in si_convert_power_state_to_smc() argument
5131 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_state_to_smc()
5132 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_convert_power_state_to_smc()
5133 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_state_to_smc()
5166 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5190 si_write_smc_soft_register(rdev, in si_convert_power_state_to_smc()
5194 si_populate_smc_sp(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5196 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5200 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5204 return si_populate_smc_t(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5207 static int si_upload_sw_state(struct radeon_device *rdev, in si_upload_sw_state() argument
5210 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_sw_state()
5222 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); in si_upload_sw_state()
5226 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_sw_state()
5232 static int si_upload_ulv_state(struct radeon_device *rdev) in si_upload_ulv_state() argument
5234 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_ulv_state()
5246 ret = si_populate_ulv_state(rdev, smc_state); in si_upload_ulv_state()
5248 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_ulv_state()
5255 static int si_upload_smc_data(struct radeon_device *rdev) in si_upload_smc_data() argument
5260 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5263 for (i = 0; i < rdev->num_crtc; i++) { in si_upload_smc_data()
5264 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5265 radeon_crtc = rdev->mode_info.crtcs[i]; in si_upload_smc_data()
5276 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5281 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5286 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5294 static int si_set_mc_special_registers(struct radeon_device *rdev, in si_set_mc_special_registers() argument
5297 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_mc_special_registers()
5471 static int si_initialize_mc_reg_table(struct radeon_device *rdev) in si_initialize_mc_reg_table() argument
5473 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_mc_reg_table()
5476 u8 module_index = rv770_get_memory_module_index(rdev); in si_initialize_mc_reg_table()
5498 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in si_initialize_mc_reg_table()
5508 ret = si_set_mc_special_registers(rdev, si_table); in si_initialize_mc_reg_table()
5521 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, in si_populate_mc_reg_addresses() argument
5524 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_addresses()
5555 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_entry_to_smc() argument
5559 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_mc_reg_table_entry_to_smc()
5575 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_to_smc() argument
5583 si_convert_mc_reg_table_entry_to_smc(rdev, in si_convert_mc_reg_table_to_smc()
5589 static int si_populate_mc_reg_table(struct radeon_device *rdev, in si_populate_mc_reg_table() argument
5593 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_table()
5599 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); in si_populate_mc_reg_table()
5601 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); in si_populate_mc_reg_table()
5603 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
5612 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, in si_populate_mc_reg_table()
5620 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); in si_populate_mc_reg_table()
5622 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
5627 static int si_upload_mc_reg_table(struct radeon_device *rdev, in si_upload_mc_reg_table() argument
5631 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_mc_reg_table()
5639 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); in si_upload_mc_reg_table()
5642 return si_copy_bytes_to_smc(rdev, address, in si_upload_mc_reg_table()
5649 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) in si_enable_voltage_control() argument
5657 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, in si_get_maximum_link_speed() argument
5672 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) in si_get_current_pcie_speed() argument
5682 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, in si_request_link_speed_change_before_state_change() argument
5686 struct si_power_info *si_pi = si_get_pi(rdev); in si_request_link_speed_change_before_state_change()
5687 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_request_link_speed_change_before_state_change()
5691 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); in si_request_link_speed_change_before_state_change()
5701 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in si_request_link_speed_change_before_state_change()
5707 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in si_request_link_speed_change_before_state_change()
5711 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); in si_request_link_speed_change_before_state_change()
5720 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, in si_notify_link_speed_change_after_state_change() argument
5724 struct si_power_info *si_pi = si_get_pi(rdev); in si_notify_link_speed_change_after_state_change()
5725 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_notify_link_speed_change_after_state_change()
5737 (si_get_current_pcie_speed(rdev) > 0)) in si_notify_link_speed_change_after_state_change()
5741 radeon_acpi_pcie_performance_request(rdev, request, false); in si_notify_link_speed_change_after_state_change()
5747 static int si_ds_request(struct radeon_device *rdev,
5750 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5754 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5758 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5765 static void si_set_max_cu_value(struct radeon_device *rdev) in si_set_max_cu_value() argument
5767 struct si_power_info *si_pi = si_get_pi(rdev); in si_set_max_cu_value()
5769 if (rdev->family == CHIP_VERDE) { in si_set_max_cu_value()
5770 switch (rdev->pdev->device) { in si_set_max_cu_value()
5806 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, in si_patch_single_dependency_table_based_on_leakage() argument
5815 switch (si_get_leakage_voltage_from_leakage_index(rdev, in si_patch_single_dependency_table_based_on_leakage()
5837 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) in si_patch_dependency_tables_based_on_leakage() argument
5841 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5843 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5844 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5845 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5846 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5850 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, in si_set_pcie_lane_width_in_smc() argument
5861 radeon_set_pcie_lanes(rdev, new_lane_width); in si_set_pcie_lane_width_in_smc()
5862 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
5867 void si_dpm_setup_asic(struct radeon_device *rdev) in si_dpm_setup_asic() argument
5871 r = si_mc_load_microcode(rdev); in si_dpm_setup_asic()
5874 rv770_get_memory_type(rdev); in si_dpm_setup_asic()
5875 si_read_clock_registers(rdev); in si_dpm_setup_asic()
5876 si_enable_acpi_power_management(rdev); in si_dpm_setup_asic()
5879 static int si_thermal_enable_alert(struct radeon_device *rdev, in si_thermal_enable_alert() argument
5889 rdev->irq.dpm_thermal = false; in si_thermal_enable_alert()
5890 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); in si_thermal_enable_alert()
5898 rdev->irq.dpm_thermal = true; in si_thermal_enable_alert()
5904 static int si_thermal_set_temperature_range(struct radeon_device *rdev, in si_thermal_set_temperature_range() argument
5923 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
5924 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
5929 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_static_mode() argument
5931 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_static_mode()
5951 static int si_thermal_setup_fan_table(struct radeon_device *rdev) in si_thermal_setup_fan_table() argument
5953 struct si_power_info *si_pi = si_get_pi(rdev); in si_thermal_setup_fan_table()
5963 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5970 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5974 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
5978 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
5979 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
5981 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
5982 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
5987 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
5988 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
5989 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
5996 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6004 reference_clock = radeon_get_xclk(rdev); in si_thermal_setup_fan_table()
6006 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6014 ret = si_copy_bytes_to_smc(rdev, in si_thermal_setup_fan_table()
6022 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6028 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_start_smc_fan_control() argument
6030 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_start_smc_fan_control()
6033 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); in si_fan_ctrl_start_smc_fan_control()
6042 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_stop_smc_fan_control() argument
6044 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_stop_smc_fan_control()
6047 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); in si_fan_ctrl_stop_smc_fan_control()
6057 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_get_fan_speed_percent() argument
6063 if (rdev->pm.no_fan) in si_fan_ctrl_get_fan_speed_percent()
6082 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_set_fan_speed_percent() argument
6085 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_fan_speed_percent()
6090 if (rdev->pm.no_fan) in si_fan_ctrl_set_fan_speed_percent()
6115 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_mode() argument
6119 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6120 si_fan_ctrl_stop_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6121 si_fan_ctrl_set_static_mode(rdev, mode); in si_fan_ctrl_set_mode()
6124 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6125 si_thermal_start_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6127 si_fan_ctrl_set_default_mode(rdev); in si_fan_ctrl_set_mode()
6131 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) in si_fan_ctrl_get_mode() argument
6133 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_get_mode()
6144 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6148 u32 xclk = radeon_get_xclk(rdev);
6150 if (rdev->pm.no_fan)
6153 if (rdev->pm.fan_pulses_per_revolution == 0)
6165 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6169 u32 xclk = radeon_get_xclk(rdev);
6171 if (rdev->pm.no_fan)
6174 if (rdev->pm.fan_pulses_per_revolution == 0)
6177 if ((speed < rdev->pm.fan_min_rpm) ||
6178 (speed > rdev->pm.fan_max_rpm))
6181 if (rdev->pm.dpm.fan.ucode_fan_control)
6182 si_fan_ctrl_stop_smc_fan_control(rdev);
6189 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6195 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) in si_fan_ctrl_set_default_mode() argument
6197 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_default_mode()
6212 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) in si_thermal_start_smc_fan_control() argument
6214 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6215 si_fan_ctrl_start_smc_fan_control(rdev); in si_thermal_start_smc_fan_control()
6216 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); in si_thermal_start_smc_fan_control()
6220 static void si_thermal_initialize(struct radeon_device *rdev) in si_thermal_initialize() argument
6224 if (rdev->pm.fan_pulses_per_revolution) { in si_thermal_initialize()
6226 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); in si_thermal_initialize()
6235 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) in si_thermal_start_thermal_controller() argument
6239 si_thermal_initialize(rdev); in si_thermal_start_thermal_controller()
6240 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_thermal_start_thermal_controller()
6243 ret = si_thermal_enable_alert(rdev, true); in si_thermal_start_thermal_controller()
6246 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6247 ret = si_halt_smc(rdev); in si_thermal_start_thermal_controller()
6250 ret = si_thermal_setup_fan_table(rdev); in si_thermal_start_thermal_controller()
6253 ret = si_resume_smc(rdev); in si_thermal_start_thermal_controller()
6256 si_thermal_start_smc_fan_control(rdev); in si_thermal_start_thermal_controller()
6262 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) in si_thermal_stop_thermal_controller() argument
6264 if (!rdev->pm.no_fan) { in si_thermal_stop_thermal_controller()
6265 si_fan_ctrl_set_default_mode(rdev); in si_thermal_stop_thermal_controller()
6266 si_fan_ctrl_stop_smc_fan_control(rdev); in si_thermal_stop_thermal_controller()
6270 int si_dpm_enable(struct radeon_device *rdev) in si_dpm_enable() argument
6272 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_enable()
6273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_enable()
6274 struct si_power_info *si_pi = si_get_pi(rdev); in si_dpm_enable()
6275 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6278 if (si_is_smc_running(rdev)) in si_dpm_enable()
6281 si_enable_voltage_control(rdev, true); in si_dpm_enable()
6283 si_get_mvdd_configuration(rdev); in si_dpm_enable()
6285 ret = si_construct_voltage_tables(rdev); in si_dpm_enable()
6292 ret = si_initialize_mc_reg_table(rdev); in si_dpm_enable()
6297 si_enable_spread_spectrum(rdev, true); in si_dpm_enable()
6299 si_enable_thermal_protection(rdev, true); in si_dpm_enable()
6300 si_setup_bsp(rdev); in si_dpm_enable()
6301 si_program_git(rdev); in si_dpm_enable()
6302 si_program_tp(rdev); in si_dpm_enable()
6303 si_program_tpp(rdev); in si_dpm_enable()
6304 si_program_sstp(rdev); in si_dpm_enable()
6305 si_enable_display_gap(rdev); in si_dpm_enable()
6306 si_program_vc(rdev); in si_dpm_enable()
6307 ret = si_upload_firmware(rdev); in si_dpm_enable()
6312 ret = si_process_firmware_header(rdev); in si_dpm_enable()
6317 ret = si_initial_switch_from_arb_f0_to_f1(rdev); in si_dpm_enable()
6322 ret = si_init_smc_table(rdev); in si_dpm_enable()
6327 ret = si_init_smc_spll_table(rdev); in si_dpm_enable()
6332 ret = si_init_arb_table_index(rdev); in si_dpm_enable()
6338 ret = si_populate_mc_reg_table(rdev, boot_ps); in si_dpm_enable()
6344 ret = si_initialize_smc_cac_tables(rdev); in si_dpm_enable()
6349 ret = si_initialize_hardware_cac_manager(rdev); in si_dpm_enable()
6354 ret = si_initialize_smc_dte_tables(rdev); in si_dpm_enable()
6359 ret = si_populate_smc_tdp_limits(rdev, boot_ps); in si_dpm_enable()
6364 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); in si_dpm_enable()
6369 si_program_response_times(rdev); in si_dpm_enable()
6370 si_program_ds_registers(rdev); in si_dpm_enable()
6371 si_dpm_start_smc(rdev); in si_dpm_enable()
6372 ret = si_notify_smc_display_change(rdev, false); in si_dpm_enable()
6377 si_enable_sclk_control(rdev, true); in si_dpm_enable()
6378 si_start_dpm(rdev); in si_dpm_enable()
6380 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in si_dpm_enable()
6382 si_thermal_start_thermal_controller(rdev); in si_dpm_enable()
6384 ni_update_current_ps(rdev, boot_ps); in si_dpm_enable()
6389 static int si_set_temperature_range(struct radeon_device *rdev) in si_set_temperature_range() argument
6393 ret = si_thermal_enable_alert(rdev, false); in si_set_temperature_range()
6396 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_set_temperature_range()
6399 ret = si_thermal_enable_alert(rdev, true); in si_set_temperature_range()
6406 int si_dpm_late_enable(struct radeon_device *rdev) in si_dpm_late_enable() argument
6410 ret = si_set_temperature_range(rdev); in si_dpm_late_enable()
6417 void si_dpm_disable(struct radeon_device *rdev) in si_dpm_disable() argument
6419 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_disable()
6420 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6422 if (!si_is_smc_running(rdev)) in si_dpm_disable()
6424 si_thermal_stop_thermal_controller(rdev); in si_dpm_disable()
6425 si_disable_ulv(rdev); in si_dpm_disable()
6426 si_clear_vc(rdev); in si_dpm_disable()
6428 si_enable_thermal_protection(rdev, false); in si_dpm_disable()
6429 si_enable_power_containment(rdev, boot_ps, false); in si_dpm_disable()
6430 si_enable_smc_cac(rdev, boot_ps, false); in si_dpm_disable()
6431 si_enable_spread_spectrum(rdev, false); in si_dpm_disable()
6432 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); in si_dpm_disable()
6433 si_stop_dpm(rdev); in si_dpm_disable()
6434 si_reset_to_default(rdev); in si_dpm_disable()
6435 si_dpm_stop_smc(rdev); in si_dpm_disable()
6436 si_force_switch_to_arb_f0(rdev); in si_dpm_disable()
6438 ni_update_current_ps(rdev, boot_ps); in si_dpm_disable()
6441 int si_dpm_pre_set_power_state(struct radeon_device *rdev) in si_dpm_pre_set_power_state() argument
6443 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_pre_set_power_state()
6444 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6447 ni_update_requested_ps(rdev, new_ps); in si_dpm_pre_set_power_state()
6449 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); in si_dpm_pre_set_power_state()
6454 static int si_power_control_set_level(struct radeon_device *rdev) in si_power_control_set_level() argument
6456 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6459 ret = si_restrict_performance_levels_before_switch(rdev); in si_power_control_set_level()
6462 ret = si_halt_smc(rdev); in si_power_control_set_level()
6465 ret = si_populate_smc_tdp_limits(rdev, new_ps); in si_power_control_set_level()
6468 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); in si_power_control_set_level()
6471 ret = si_resume_smc(rdev); in si_power_control_set_level()
6474 ret = si_set_sw_state(rdev); in si_power_control_set_level()
6480 int si_dpm_set_power_state(struct radeon_device *rdev) in si_dpm_set_power_state() argument
6482 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_set_power_state()
6487 ret = si_disable_ulv(rdev); in si_dpm_set_power_state()
6492 ret = si_restrict_performance_levels_before_switch(rdev); in si_dpm_set_power_state()
6498 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6499 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6500 ret = si_enable_power_containment(rdev, new_ps, false); in si_dpm_set_power_state()
6505 ret = si_enable_smc_cac(rdev, new_ps, false); in si_dpm_set_power_state()
6510 ret = si_halt_smc(rdev); in si_dpm_set_power_state()
6515 ret = si_upload_sw_state(rdev, new_ps); in si_dpm_set_power_state()
6520 ret = si_upload_smc_data(rdev); in si_dpm_set_power_state()
6525 ret = si_upload_ulv_state(rdev); in si_dpm_set_power_state()
6531 ret = si_upload_mc_reg_table(rdev, new_ps); in si_dpm_set_power_state()
6537 ret = si_program_memory_timing_parameters(rdev, new_ps); in si_dpm_set_power_state()
6542 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6544 ret = si_resume_smc(rdev); in si_dpm_set_power_state()
6549 ret = si_set_sw_state(rdev); in si_dpm_set_power_state()
6554 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6556 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6557 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); in si_dpm_set_power_state()
6562 ret = si_enable_smc_cac(rdev, new_ps, true); in si_dpm_set_power_state()
6567 ret = si_enable_power_containment(rdev, new_ps, true); in si_dpm_set_power_state()
6573 ret = si_power_control_set_level(rdev); in si_dpm_set_power_state()
6582 void si_dpm_post_set_power_state(struct radeon_device *rdev) in si_dpm_post_set_power_state() argument
6584 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_post_set_power_state()
6587 ni_update_current_ps(rdev, new_ps); in si_dpm_post_set_power_state()
6591 void si_dpm_reset_asic(struct radeon_device *rdev)
6593 si_restrict_performance_levels_before_switch(rdev);
6594 si_disable_ulv(rdev);
6595 si_set_boot_state(rdev);
6599 void si_dpm_display_configuration_changed(struct radeon_device *rdev) in si_dpm_display_configuration_changed() argument
6601 si_program_display_gap(rdev); in si_dpm_display_configuration_changed()
6626 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, in si_parse_pplib_non_clock_info() argument
6647 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6649 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6652 static void si_parse_pplib_clock_info(struct radeon_device *rdev, in si_parse_pplib_clock_info() argument
6656 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_parse_pplib_clock_info()
6657 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_parse_pplib_clock_info()
6658 struct si_power_info *si_pi = si_get_pi(rdev); in si_parse_pplib_clock_info()
6674 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in si_parse_pplib_clock_info()
6680 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6711 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6712 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6713 pl->sclk = rdev->clock.default_sclk; in si_parse_pplib_clock_info()
6721 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6722 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6723 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6724 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6728 static int si_parse_power_table(struct radeon_device *rdev) in si_parse_power_table() argument
6730 struct radeon_mode_info *mode_info = &rdev->mode_info; in si_parse_power_table()
6760 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in si_parse_power_table()
6762 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6771 if (!rdev->pm.power_state[i].clock_info) in si_parse_power_table()
6775 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6778 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6779 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6793 si_parse_pplib_clock_info(rdev, in si_parse_power_table()
6794 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6800 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6804 int si_dpm_init(struct radeon_device *rdev) in si_dpm_init() argument
6817 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6822 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); in si_dpm_init()
6828 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); in si_dpm_init()
6830 si_set_max_cu_value(rdev); in si_dpm_init()
6832 rv770_get_max_vddc(rdev); in si_dpm_init()
6833 si_get_leakage_vddc(rdev); in si_dpm_init()
6834 si_patch_dependency_tables_based_on_leakage(rdev); in si_dpm_init()
6841 ret = r600_get_platform_caps(rdev); in si_dpm_init()
6845 ret = si_parse_power_table(rdev); in si_dpm_init()
6848 ret = r600_parse_extended_power_table(rdev); in si_dpm_init()
6852 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6854 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6855 r600_free_extended_power_table(rdev); in si_dpm_init()
6858 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6859 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6860 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6861 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6862 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6863 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6864 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6865 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6866 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6868 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6869 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6870 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6871 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
6873 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_dpm_init()
6883 if (si_is_special_1gb_platform(rdev)) in si_dpm_init()
6893 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6897 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6900 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6905 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, in si_dpm_init()
6909 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
6913 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
6917 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6920 rv770_get_engine_memory_ss(rdev); in si_dpm_init()
6931 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in si_dpm_init()
6941 radeon_acpi_is_pcie_performance_request_supported(rdev); in si_dpm_init()
6948 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
6949 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
6950 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
6951 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
6952 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
6953 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
6954 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
6956 si_initialize_powertune_defaults(rdev); in si_dpm_init()
6959 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
6960 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
6961 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
6962 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
6969 void si_dpm_fini(struct radeon_device *rdev) in si_dpm_fini() argument
6973 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
6974 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
6976 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
6977 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
6978 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
6979 r600_free_extended_power_table(rdev); in si_dpm_fini()
6982 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in si_dpm_debugfs_print_current_performance_level() argument
6985 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_debugfs_print_current_performance_level()
7003 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) in si_dpm_get_current_sclk() argument
7005 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_sclk()
7021 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) in si_dpm_get_current_mclk() argument
7023 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_mclk()