1764         struct si_power_info *pi = rdev->pm.dpm.priv;  in si_get_pi()
1838 	u32 p_limit1 = rdev->pm.dpm.tdp_limit;  in si_update_dte_from_pl2()
1839 	u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;  in si_update_dte_from_pl2()
2128 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in si_calculate_adjusted_tdp_limits()
2131 	max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2134 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2135 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in si_calculate_adjusted_tdp_limits()
2137 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2138 		adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;  in si_calculate_adjusted_tdp_limits()
2139 		if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)  in si_calculate_adjusted_tdp_limits()
2140 			*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;  in si_calculate_adjusted_tdp_limits()
2162 		struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;  in si_populate_smc_tdp_limits()
2175 						       rdev->pm.dpm.tdp_adjustment,  in si_populate_smc_tdp_limits()
2232 			cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);  in si_populate_smc_tdp_limits_2()
2234 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_…  in si_populate_smc_tdp_limits_2()
2394 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in si_populate_sq_ramping_values()
2416 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in si_populate_sq_ramping_values()
2535 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in si_get_cac_std_voltage_max_min()
2672 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2699 	load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;  in si_initialize_smc_cac_tables()
2963 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in si_apply_state_adjust_rules()
2972 	if (rdev->pm.dpm.ac_power)  in si_apply_state_adjust_rules()
2973 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_apply_state_adjust_rules()
2975 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in si_apply_state_adjust_rules()
2981 	if (rdev->pm.dpm.ac_power == false) {  in si_apply_state_adjust_rules()
2995 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
2997 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
2999 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3092 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
3095 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
3098 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3101 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in si_apply_state_adjust_rules()
3115 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in si_apply_state_adjust_rules()
3342 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()
3366 	rdev->pm.dpm.forced_level = level;  in si_dpm_force_performance_level()
3587 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in si_program_response_times()
3588         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;  in si_program_response_times()
3626 	if (rdev->pm.dpm.new_active_crtc_count > 0)  in si_program_display_gap()
3631 	if (rdev->pm.dpm.new_active_crtc_count > 1)  in si_program_display_gap()
3641 	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&  in si_program_display_gap()
3642 	    (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {  in si_program_display_gap()
3645 			if (rdev->pm.dpm.new_active_crtcs & (1 << i))  in si_program_display_gap()
3662 	si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);  in si_program_display_gap()
3915 						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_construct_voltage_tables()
3936 						&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_construct_voltage_tables()
4032 							      &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {  in si_populate_smc_voltage_tables()
4094 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {  in si_get_std_voltage_value()
4095 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {  in si_get_std_voltage_value()
4096 			if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)  in si_get_std_voltage_value()
4099 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4101 				    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4103 					if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4105 							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4108 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4114 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4116 					    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4118 						if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4120 								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4123 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4129 			if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4130 				*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in si_get_std_voltage_value()
4382 						 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_initial_state()
4468 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4495 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4636 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in si_init_smc_table()
4645 	switch (rdev->pm.int_thermal_type) {  in si_init_smc_table()
4658 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in si_init_smc_table()
4661 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {  in si_init_smc_table()
4666 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in si_init_smc_table()
4672 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)  in si_init_smc_table()
4675 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {  in si_init_smc_table()
4677 		vr_hot_gpio = rdev->pm.dpm.backbias_response_time;  in si_init_smc_table()
4943 	    (rdev->pm.dpm.new_active_crtc_count <= 2)) {  in si_convert_power_level_to_smc()
5008 						       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_convert_power_level_to_smc()
5098 	for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {  in si_is_state_ulv_compatible()
5100 		    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {  in si_is_state_ulv_compatible()
5102 			    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)  in si_is_state_ulv_compatible()
5260 	if (rdev->pm.dpm.new_active_crtc_count == 0)  in si_upload_smc_data()
5264 		if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {  in si_upload_smc_data()
5842 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in si_patch_dependency_tables_based_on_leakage()
5844 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
5846 								&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
5923 	rdev->pm.dpm.thermal.min_temp = low_temp;  in si_thermal_set_temperature_range()
5924 	rdev->pm.dpm.thermal.max_temp = high_temp;  in si_thermal_set_temperature_range()
5963 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
5970 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
5974 	tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;  in si_thermal_setup_fan_table()
5978 	t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;  in si_thermal_setup_fan_table()
5979 	t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;  in si_thermal_setup_fan_table()
5981 	pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;  in si_thermal_setup_fan_table()
5982 	pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;  in si_thermal_setup_fan_table()
5987 	fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);  in si_thermal_setup_fan_table()
5988 	fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);  in si_thermal_setup_fan_table()
5989 	fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);  in si_thermal_setup_fan_table()
5996 	fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);  in si_thermal_setup_fan_table()
6006 	fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *  in si_thermal_setup_fan_table()
6022 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6063 	if (rdev->pm.no_fan)  in si_fan_ctrl_get_fan_speed_percent()
6090 	if (rdev->pm.no_fan)  in si_fan_ctrl_set_fan_speed_percent()
6119 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6124 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6150 	if (rdev->pm.no_fan)
6153 	if (rdev->pm.fan_pulses_per_revolution == 0)
6171 	if (rdev->pm.no_fan)
6174 	if (rdev->pm.fan_pulses_per_revolution == 0)
6177 	if ((speed < rdev->pm.fan_min_rpm) ||
6178 	    (speed > rdev->pm.fan_max_rpm))
6181 	if (rdev->pm.dpm.fan.ucode_fan_control)
6214 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_smc_fan_control()
6224 	if (rdev->pm.fan_pulses_per_revolution) {  in si_thermal_initialize()
6226 		tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);  in si_thermal_initialize()
6246 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_thermal_controller()
6264 	if (!rdev->pm.no_fan) {  in si_thermal_stop_thermal_controller()
6275 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_enable()
6420 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_disable()
6444 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in si_dpm_pre_set_power_state()
6456 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in si_power_control_set_level()
6647 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6649 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6721 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6722 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in si_parse_pplib_clock_info()
6723 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in si_parse_pplib_clock_info()
6724 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in si_parse_pplib_clock_info()
6760 	rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *  in si_parse_power_table()
6762 	if (!rdev->pm.dpm.ps)  in si_parse_power_table()
6771 		if (!rdev->pm.power_state[i].clock_info)  in si_parse_power_table()
6775 			kfree(rdev->pm.dpm.ps);  in si_parse_power_table()
6778 		rdev->pm.dpm.ps[i].ps_priv = ps;  in si_parse_power_table()
6779 		si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in si_parse_power_table()
6794 						  &rdev->pm.dpm.ps[i], k,  in si_parse_power_table()
6800 	rdev->pm.dpm.num_ps = state_array->ucNumEntries;  in si_parse_power_table()
6817 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6852 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in si_dpm_init()
6854 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in si_dpm_init()
6858 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in si_dpm_init()
6859 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in si_dpm_init()
6860 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in si_dpm_init()
6861 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in si_dpm_init()
6862 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in si_dpm_init()
6863 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in si_dpm_init()
6864 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in si_dpm_init()
6865 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in si_dpm_init()
6866 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in si_dpm_init()
6868 	if (rdev->pm.dpm.voltage_response_time == 0)  in si_dpm_init()
6869 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in si_dpm_init()
6870 	if (rdev->pm.dpm.backbias_response_time == 0)  in si_dpm_init()
6871 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in si_dpm_init()
6931 	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)  in si_dpm_init()
6948 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;  in si_dpm_init()
6949 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;  in si_dpm_init()
6950 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in si_dpm_init()
6951 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;  in si_dpm_init()
6952 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;  in si_dpm_init()
6953 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in si_dpm_init()
6954 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in si_dpm_init()
6959 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in si_dpm_init()
6960 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in si_dpm_init()
6961 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in si_dpm_init()
6962 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_dpm_init()
6973 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in si_dpm_fini()
6974 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in si_dpm_fini()
6976 	kfree(rdev->pm.dpm.ps);  in si_dpm_fini()
6977 	kfree(rdev->pm.dpm.priv);  in si_dpm_fini()
6978 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in si_dpm_fini()