Lines Matching refs:rlc
5205 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5210 if (tmp != rlc) in si_update_rlc()
5211 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5267 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5273 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5673 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5681 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5705 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5717 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5769 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5770 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5775 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5776 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
6900 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6901 rdev->rlc.reg_list_size = in si_startup()
6904 rdev->rlc.cs_data = si_cs_data; in si_startup()