Lines Matching refs:ring
3371 struct radeon_ring *ring = &rdev->ring[fence->ring]; in si_fence_ring_emit() local
3372 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
3375 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3376 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3377 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3378 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3379 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_fence_ring_emit()
3383 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
3384 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3385 radeon_ring_write(ring, 10); /* poll interval */ in si_fence_ring_emit()
3387 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3388 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in si_fence_ring_emit()
3389 radeon_ring_write(ring, lower_32_bits(addr)); in si_fence_ring_emit()
3390 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
3391 radeon_ring_write(ring, fence->seq); in si_fence_ring_emit()
3392 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3400 struct radeon_ring *ring = &rdev->ring[ib->ring]; in si_ring_ib_execute() local
3401 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in si_ring_ib_execute()
3406 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3407 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3412 if (ring->rptr_save_reg) { in si_ring_ib_execute()
3413 next_rptr = ring->wptr + 3 + 4 + 8; in si_ring_ib_execute()
3414 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3415 radeon_ring_write(ring, ((ring->rptr_save_reg - in si_ring_ib_execute()
3417 radeon_ring_write(ring, next_rptr); in si_ring_ib_execute()
3419 next_rptr = ring->wptr + 5 + 4 + 8; in si_ring_ib_execute()
3420 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3421 radeon_ring_write(ring, (1 << 8)); in si_ring_ib_execute()
3422 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in si_ring_ib_execute()
3423 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in si_ring_ib_execute()
3424 radeon_ring_write(ring, next_rptr); in si_ring_ib_execute()
3430 radeon_ring_write(ring, header); in si_ring_ib_execute()
3431 radeon_ring_write(ring, in si_ring_ib_execute()
3436 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
3437 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in si_ring_ib_execute()
3441 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3442 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()
3443 radeon_ring_write(ring, vm_id); in si_ring_ib_execute()
3444 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
3445 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_ring_ib_execute()
3449 radeon_ring_write(ring, 0xFFFFFFFF); in si_ring_ib_execute()
3450 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3451 radeon_ring_write(ring, 10); /* poll interval */ in si_ring_ib_execute()
3467 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_enable()
3468 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_enable()
3469 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_enable()
3557 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_start() local
3560 r = radeon_ring_lock(rdev, ring, 7 + 4); in si_cp_start()
3566 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in si_cp_start()
3567 radeon_ring_write(ring, 0x1); in si_cp_start()
3568 radeon_ring_write(ring, 0x0); in si_cp_start()
3569 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); in si_cp_start()
3570 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in si_cp_start()
3571 radeon_ring_write(ring, 0); in si_cp_start()
3572 radeon_ring_write(ring, 0); in si_cp_start()
3575 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
3576 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in si_cp_start()
3577 radeon_ring_write(ring, 0xc000); in si_cp_start()
3578 radeon_ring_write(ring, 0xe000); in si_cp_start()
3579 radeon_ring_unlock_commit(rdev, ring, false); in si_cp_start()
3583 r = radeon_ring_lock(rdev, ring, si_default_size + 10); in si_cp_start()
3590 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3591 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
3594 radeon_ring_write(ring, si_default_state[i]); in si_cp_start()
3596 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3597 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
3600 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3601 radeon_ring_write(ring, 0); in si_cp_start()
3603 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in si_cp_start()
3604 radeon_ring_write(ring, 0x00000316); in si_cp_start()
3605 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in si_cp_start()
3606 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in si_cp_start()
3608 radeon_ring_unlock_commit(rdev, ring, false); in si_cp_start()
3611 ring = &rdev->ring[i]; in si_cp_start()
3612 r = radeon_ring_lock(rdev, ring, 2); in si_cp_start()
3615 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3616 radeon_ring_write(ring, 0); in si_cp_start()
3618 radeon_ring_unlock_commit(rdev, ring, false); in si_cp_start()
3626 struct radeon_ring *ring; in si_cp_fini() local
3629 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_fini()
3630 radeon_ring_fini(rdev, ring); in si_cp_fini()
3631 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3633 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_fini()
3634 radeon_ring_fini(rdev, ring); in si_cp_fini()
3635 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3637 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_fini()
3638 radeon_ring_fini(rdev, ring); in si_cp_fini()
3639 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3644 struct radeon_ring *ring; in si_cp_resume() local
3662 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_resume()
3663 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3672 ring->wptr = 0; in si_cp_resume()
3673 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3689 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3693 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_resume()
3694 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3703 ring->wptr = 0; in si_cp_resume()
3704 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3713 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3717 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_resume()
3718 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3727 ring->wptr = 0; in si_cp_resume()
3728 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3737 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3741 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in si_cp_resume()
3742 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; in si_cp_resume()
3743 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; in si_cp_resume()
3744 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in si_cp_resume()
3746 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_resume()
3747 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3748 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
3751 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in si_cp_resume()
3753 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3755 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); in si_cp_resume()
3757 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
4116 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in si_gfx_is_lockup() argument
4123 radeon_ring_lockup_update(rdev, ring); in si_gfx_is_lockup()
4126 return radeon_ring_test_lockup(rdev, ring); in si_gfx_is_lockup()
4744 switch (ib->ring) { in si_ib_parse()
4753 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); in si_ib_parse()
5060 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in si_vm_flush() argument
5064 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5065 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5069 radeon_ring_write(ring, in si_vm_flush()
5072 radeon_ring_write(ring, in si_vm_flush()
5075 radeon_ring_write(ring, 0); in si_vm_flush()
5076 radeon_ring_write(ring, pd_addr >> 12); in si_vm_flush()
5079 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5080 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5082 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); in si_vm_flush()
5083 radeon_ring_write(ring, 0); in si_vm_flush()
5084 radeon_ring_write(ring, 0x1); in si_vm_flush()
5087 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5088 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5090 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in si_vm_flush()
5091 radeon_ring_write(ring, 0); in si_vm_flush()
5092 radeon_ring_write(ring, 1 << vm_id); in si_vm_flush()
5095 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
5096 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in si_vm_flush()
5098 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in si_vm_flush()
5099 radeon_ring_write(ring, 0); in si_vm_flush()
5100 radeon_ring_write(ring, 0); /* ref */ in si_vm_flush()
5101 radeon_ring_write(ring, 0); /* mask */ in si_vm_flush()
5102 radeon_ring_write(ring, 0x20); /* poll interval */ in si_vm_flush()
5105 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in si_vm_flush()
5106 radeon_ring_write(ring, 0x0); in si_vm_flush()
6461 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in si_irq_process()
6462 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in si_irq_process()
6463 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; in si_irq_process()
6870 struct radeon_ring *ring; in si_startup() local
6955 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in si_startup()
6973 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_startup()
6974 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in si_startup()
6979 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_startup()
6980 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, in si_startup()
6985 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_startup()
6986 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, in si_startup()
6991 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_startup()
6992 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in si_startup()
6997 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_startup()
6998 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in si_startup()
7015 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in si_startup()
7016 if (ring->ring_size) { in si_startup()
7017 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in si_startup()
7101 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init() local
7162 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init()
7163 ring->ring_obj = NULL; in si_init()
7164 r600_ring_init(rdev, ring, 1024 * 1024); in si_init()
7166 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_init()
7167 ring->ring_obj = NULL; in si_init()
7168 r600_ring_init(rdev, ring, 1024 * 1024); in si_init()
7170 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_init()
7171 ring->ring_obj = NULL; in si_init()
7172 r600_ring_init(rdev, ring, 1024 * 1024); in si_init()
7174 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_init()
7175 ring->ring_obj = NULL; in si_init()
7176 r600_ring_init(rdev, ring, 64 * 1024); in si_init()
7178 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_init()
7179 ring->ring_obj = NULL; in si_init()
7180 r600_ring_init(rdev, ring, 64 * 1024); in si_init()
7185 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in si_init()
7186 ring->ring_obj = NULL; in si_init()
7187 r600_ring_init(rdev, ring, 4096); in si_init()