4442 				  u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_ce_check()  argument
4444 	switch (pkt->opcode) {  in si_vm_packet3_ce_check()
4457 		DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_ce_check()
4515 				   u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_gfx_check()  argument
4518 	u32 idx = pkt->idx + 1;  in si_vm_packet3_gfx_check()
4522 	switch (pkt->opcode) {  in si_vm_packet3_gfx_check()
4583 				for (i = 0; i < (pkt->count - 2); i++) {  in si_vm_packet3_gfx_check()
4607 		end_reg = 4 * pkt->count + start_reg - 4;  in si_vm_packet3_gfx_check()
4614 		for (i = 0; i < pkt->count; i++) {  in si_vm_packet3_gfx_check()
4626 		DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_gfx_check()
4633 				       u32 *ib, struct radeon_cs_packet *pkt)  in si_vm_packet3_compute_check()  argument
4636 	u32 idx = pkt->idx + 1;  in si_vm_packet3_compute_check()
4640 	switch (pkt->opcode) {  in si_vm_packet3_compute_check()
4686 				for (i = 0; i < (pkt->count - 2); i++) {  in si_vm_packet3_compute_check()
4714 		DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);  in si_vm_packet3_compute_check()
4724 	struct radeon_cs_packet pkt;  in si_ib_parse()  local
4727 		pkt.idx = idx;  in si_ib_parse()
4728 		pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);  in si_ib_parse()
4729 		pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);  in si_ib_parse()
4730 		pkt.one_reg_wr = 0;  in si_ib_parse()
4731 		switch (pkt.type) {  in si_ib_parse()
4740 			pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);  in si_ib_parse()
4742 				ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4746 					ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4750 					ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);  in si_ib_parse()
4758 			idx += pkt.count + 2;  in si_ib_parse()
4761 			dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);  in si_ib_parse()