Lines Matching refs:INT_MASK
5948 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5949 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5952 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5953 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5956 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5957 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
6194 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
6195 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
6198 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
6199 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in si_irq_set()
6202 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in si_irq_set()
6203 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()