Lines Matching refs:tmp
1311 u32 tmp; in si_get_xclk() local
1313 tmp = RREG32(CG_CLKPIN_CNTL_2); in si_get_xclk()
1314 if (tmp & MUX_TCLK_TO_XCLK) in si_get_xclk()
1317 tmp = RREG32(CG_CLKPIN_CNTL); in si_get_xclk()
1318 if (tmp & XTALIN_DIVIDE) in si_get_xclk()
1916 u32 tmp, buffer_alloc, i; in dce6_line_buffer_adjust() local
1933 tmp = 0; /* 1/2 */ in dce6_line_buffer_adjust()
1936 tmp = 2; /* whole */ in dce6_line_buffer_adjust()
1940 tmp = 0; in dce6_line_buffer_adjust()
1945 DC_LB_MEMORY_CONFIG(tmp)); in dce6_line_buffer_adjust()
1957 switch (tmp) { in dce6_line_buffer_adjust()
1972 u32 tmp = RREG32(MC_SHARED_CHMAP); in si_get_number_of_dram_channels() local
1974 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in si_get_number_of_dram_channels()
2156 u32 tmp, dmif_size = 12288; in dce6_latency_watermark() local
2183 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); in dce6_latency_watermark()
2191 lb_fill_bw = min(tmp, dfixed_trunc(b)); in dce6_latency_watermark()
2264 u32 tmp, arb_control3; in dce6_program_watermarks() local
2383 tmp = arb_control3; in dce6_program_watermarks()
2384 tmp &= ~LATENCY_WATERMARK_MASK(3); in dce6_program_watermarks()
2385 tmp |= LATENCY_WATERMARK_MASK(1); in dce6_program_watermarks()
2386 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2391 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2392 tmp &= ~LATENCY_WATERMARK_MASK(3); in dce6_program_watermarks()
2393 tmp |= LATENCY_WATERMARK_MASK(2); in dce6_program_watermarks()
2394 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
3093 u32 tmp; in si_gpu_init() local
3207 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; in si_gpu_init()
3208 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in si_gpu_init()
3341 tmp = RREG32(HDP_MISC_CNTL); in si_gpu_init()
3342 tmp |= HDP_FLUSH_INVALIDATE_CACHE; in si_gpu_init()
3343 WREG32(HDP_MISC_CNTL, tmp); in si_gpu_init()
3645 u32 tmp; in si_cp_resume() local
3664 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3666 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3668 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3671 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3682 tmp |= RB_NO_UPDATE; in si_cp_resume()
3687 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3695 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3697 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3699 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3702 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3711 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3719 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3721 tmp |= BUF_SWAP_32BIT; in si_cp_resume()
3723 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3726 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3735 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3771 u32 tmp; in si_gpu_check_soft_reset() local
3774 tmp = RREG32(GRBM_STATUS); in si_gpu_check_soft_reset()
3775 if (tmp & (PA_BUSY | SC_BUSY | in si_gpu_check_soft_reset()
3783 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | in si_gpu_check_soft_reset()
3787 if (tmp & GRBM_EE_BUSY) in si_gpu_check_soft_reset()
3791 tmp = RREG32(GRBM_STATUS2); in si_gpu_check_soft_reset()
3792 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) in si_gpu_check_soft_reset()
3796 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3797 if (!(tmp & DMA_IDLE)) in si_gpu_check_soft_reset()
3801 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3802 if (!(tmp & DMA_IDLE)) in si_gpu_check_soft_reset()
3806 tmp = RREG32(SRBM_STATUS2); in si_gpu_check_soft_reset()
3807 if (tmp & DMA_BUSY) in si_gpu_check_soft_reset()
3810 if (tmp & DMA1_BUSY) in si_gpu_check_soft_reset()
3814 tmp = RREG32(SRBM_STATUS); in si_gpu_check_soft_reset()
3816 if (tmp & IH_BUSY) in si_gpu_check_soft_reset()
3819 if (tmp & SEM_BUSY) in si_gpu_check_soft_reset()
3822 if (tmp & GRBM_RQ_PENDING) in si_gpu_check_soft_reset()
3825 if (tmp & VMC_BUSY) in si_gpu_check_soft_reset()
3828 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | in si_gpu_check_soft_reset()
3836 tmp = RREG32(VM_L2_STATUS); in si_gpu_check_soft_reset()
3837 if (tmp & L2_BUSY) in si_gpu_check_soft_reset()
3853 u32 tmp; in si_gpu_soft_reset() local
3878 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3879 tmp &= ~DMA_RB_ENABLE; in si_gpu_soft_reset()
3880 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3884 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3885 tmp &= ~DMA_RB_ENABLE; in si_gpu_soft_reset()
3886 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3945 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3946 tmp |= grbm_soft_reset; in si_gpu_soft_reset()
3947 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3948 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3949 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3953 tmp &= ~grbm_soft_reset; in si_gpu_soft_reset()
3954 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3955 tmp = RREG32(GRBM_SOFT_RESET); in si_gpu_soft_reset()
3959 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3960 tmp |= srbm_soft_reset; in si_gpu_soft_reset()
3961 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3962 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3963 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3967 tmp &= ~srbm_soft_reset; in si_gpu_soft_reset()
3968 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3969 tmp = RREG32(SRBM_SOFT_RESET); in si_gpu_soft_reset()
3983 u32 tmp, i; in si_set_clk_bypass_mode() local
3985 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3986 tmp |= SPLL_BYPASS_EN; in si_set_clk_bypass_mode()
3987 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
3989 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3990 tmp |= SPLL_CTLREQ_CHG; in si_set_clk_bypass_mode()
3991 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
3999 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4000 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); in si_set_clk_bypass_mode()
4001 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4003 tmp = RREG32(MPLL_CNTL_MODE); in si_set_clk_bypass_mode()
4004 tmp &= ~MPLL_MCLK_SEL; in si_set_clk_bypass_mode()
4005 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
4010 u32 tmp; in si_spll_powerdown() local
4012 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4013 tmp |= SPLL_SW_DIR_CONTROL; in si_spll_powerdown()
4014 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4016 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4017 tmp |= SPLL_RESET; in si_spll_powerdown()
4018 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4020 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4021 tmp |= SPLL_SLEEP; in si_spll_powerdown()
4022 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4024 tmp = RREG32(SPLL_CNTL_MODE); in si_spll_powerdown()
4025 tmp &= ~SPLL_SW_DIR_CONTROL; in si_spll_powerdown()
4026 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4032 u32 tmp, i; in si_gpu_pci_config_reset() local
4045 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4046 tmp &= ~DMA_RB_ENABLE; in si_gpu_pci_config_reset()
4047 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4049 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4050 tmp &= ~DMA_RB_ENABLE; in si_gpu_pci_config_reset()
4051 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4133 u32 tmp; in si_mc_program() local
4160 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in si_mc_program()
4161 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in si_mc_program()
4162 WREG32(MC_VM_FB_LOCATION, tmp); in si_mc_program()
4197 u32 tmp; in si_mc_init() local
4202 tmp = RREG32(MC_ARB_RAMCFG); in si_mc_init()
4203 if (tmp & CHANSIZE_OVERRIDE) { in si_mc_init()
4205 } else if (tmp & CHANSIZE_MASK) { in si_mc_init()
4210 tmp = RREG32(MC_SHARED_CHMAP); in si_mc_init()
4211 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in si_mc_init()
4246 tmp = RREG32(CONFIG_MEMSIZE); in si_mc_init()
4248 if (tmp & 0xffff0000) { in si_mc_init()
4249 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in si_mc_init()
4250 if (tmp & 0xffff) in si_mc_init()
4251 tmp &= 0xffff; in si_mc_init()
4253 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; in si_mc_init()
5132 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt() local
5137 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5139 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5140 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5144 tmp = RREG32(DB_DEPTH_INFO); in si_enable_gui_idle_interrupt()
5158 u32 tmp, tmp2; in si_set_uvd_dcm() local
5160 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm()
5161 tmp &= ~(CLK_OD_MASK | CG_DT_MASK); in si_set_uvd_dcm()
5162 tmp |= DCM | CG_DT(1) | CLK_OD(4); in si_set_uvd_dcm()
5165 tmp &= ~0x7ffff800; in si_set_uvd_dcm()
5168 tmp |= 0x7ffff800; in si_set_uvd_dcm()
5172 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5183 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg() local
5184 tmp &= ~DCM; in si_init_uvd_internal_cg()
5185 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5207 u32 tmp; in si_update_rlc() local
5209 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5210 if (tmp != rlc) in si_update_rlc()
5229 u32 tmp; in si_init_dma_pg() local
5234 for (tmp = 0; tmp < 5; tmp++) in si_init_dma_pg()
5241 u32 tmp; in si_enable_gfx_cgpg() local
5244 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); in si_enable_gfx_cgpg()
5245 WREG32(RLC_TTOP_D, tmp); in si_enable_gfx_cgpg()
5247 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5248 tmp |= GFX_PG_ENABLE; in si_enable_gfx_cgpg()
5249 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5251 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5252 tmp |= AUTO_PG_EN; in si_enable_gfx_cgpg()
5253 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5255 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_enable_gfx_cgpg()
5256 tmp &= ~AUTO_PG_EN; in si_enable_gfx_cgpg()
5257 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5259 tmp = RREG32(DB_RENDER_CONTROL); in si_enable_gfx_cgpg()
5265 u32 tmp; in si_init_gfx_cgpg() local
5269 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5270 tmp |= GFX_PG_SRC; in si_init_gfx_cgpg()
5271 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
5275 tmp = RREG32(RLC_AUTO_PG_CTRL); in si_init_gfx_cgpg()
5277 tmp &= ~GRBM_REG_SGIT_MASK; in si_init_gfx_cgpg()
5278 tmp |= GRBM_REG_SGIT(0x700); in si_init_gfx_cgpg()
5279 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; in si_init_gfx_cgpg()
5280 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_init_gfx_cgpg()
5285 u32 mask = 0, tmp, tmp1; in si_get_cu_active_bitmap() local
5289 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in si_get_cu_active_bitmap()
5293 tmp &= 0xffff0000; in si_get_cu_active_bitmap()
5295 tmp |= tmp1; in si_get_cu_active_bitmap()
5296 tmp >>= 16; in si_get_cu_active_bitmap()
5303 return (~tmp) & mask; in si_get_cu_active_bitmap()
5310 u32 tmp = 0; in si_init_ao_cu_mask() local
5327 tmp |= (cu_bitmap << (i * 16 + j * 8)); in si_init_ao_cu_mask()
5331 WREG32(RLC_PG_AO_CU_MASK, tmp); in si_init_ao_cu_mask()
5333 tmp = RREG32(RLC_MAX_PG_CU); in si_init_ao_cu_mask()
5334 tmp &= ~MAX_PU_CU_MASK; in si_init_ao_cu_mask()
5335 tmp |= MAX_PU_CU(active_cu_number); in si_init_ao_cu_mask()
5336 WREG32(RLC_MAX_PG_CU, tmp); in si_init_ao_cu_mask()
5342 u32 data, orig, tmp; in si_enable_cgcg() local
5351 tmp = si_halt_rlc(rdev); in si_enable_cgcg()
5359 si_update_rlc(rdev, tmp); in si_enable_cgcg()
5382 u32 data, orig, tmp = 0; in si_enable_mgcg() local
5402 tmp = si_halt_rlc(rdev); in si_enable_mgcg()
5408 si_update_rlc(rdev, tmp); in si_enable_mgcg()
5425 tmp = si_halt_rlc(rdev); in si_enable_mgcg()
5431 si_update_rlc(rdev, tmp); in si_enable_mgcg()
5438 u32 orig, data, tmp; in si_enable_uvd_mgcg() local
5441 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5442 tmp |= 0x3fff; in si_enable_uvd_mgcg()
5443 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
5453 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5454 tmp &= ~0x3fff; in si_enable_uvd_mgcg()
5455 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
5793 u32 tmp = RREG32(GRBM_SOFT_RESET); in si_rlc_reset() local
5795 tmp |= SOFT_RESET_RLC; in si_rlc_reset()
5796 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5798 tmp &= ~SOFT_RESET_RLC; in si_rlc_reset()
5799 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5823 u32 tmp; in si_lbpw_supported() local
5826 tmp = RREG32(MC_SEQ_MISC0); in si_lbpw_supported()
5827 if ((tmp & 0xF0000000) == 0xB0000000) in si_lbpw_supported()
5834 u32 tmp; in si_enable_lbpw() local
5836 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5838 tmp |= LOAD_BALANCE_ENABLE; in si_enable_lbpw()
5840 tmp &= ~LOAD_BALANCE_ENABLE; in si_enable_lbpw()
5841 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5934 u32 tmp; in si_disable_interrupt_state() local
5936 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5938 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
5941 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5942 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5943 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5944 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5976 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5977 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state()
5978 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5979 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_disable_interrupt_state()
5980 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5981 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_disable_interrupt_state()
5982 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5983 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_disable_interrupt_state()
5984 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5985 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_disable_interrupt_state()
5986 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5987 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_disable_interrupt_state()
6244 u32 tmp; in si_irq_ack() local
6310 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6311 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6312 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6315 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6316 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6317 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6320 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6321 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6322 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6325 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6326 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6327 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6330 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6331 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6332 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6335 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6336 tmp |= DC_HPDx_INT_ACK; in si_irq_ack()
6337 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6341 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6342 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6343 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6346 tmp = RREG32(DC_HPD2_INT_CONTROL); in si_irq_ack()
6347 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6348 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6351 tmp = RREG32(DC_HPD3_INT_CONTROL); in si_irq_ack()
6352 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6353 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6356 tmp = RREG32(DC_HPD4_INT_CONTROL); in si_irq_ack()
6357 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6358 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6361 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6362 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6363 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6366 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6367 tmp |= DC_HPDx_RX_INT_ACK; in si_irq_ack()
6368 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6395 u32 wptr, tmp; in si_get_ih_wptr() local
6411 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6412 tmp |= IH_WPTR_OVERFLOW_CLEAR; in si_get_ih_wptr()
6413 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
7419 u32 max_lw, current_lw, tmp; in si_pcie_gen3_enable() local
7430 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7431 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; in si_pcie_gen3_enable()
7432 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; in si_pcie_gen3_enable()
7435 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_pcie_gen3_enable()
7436 if (tmp & LC_RENEGOTIATION_SUPPORT) { in si_pcie_gen3_enable()
7437 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); in si_pcie_gen3_enable()
7438 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); in si_pcie_gen3_enable()
7439 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; in si_pcie_gen3_enable()
7440 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); in si_pcie_gen3_enable()
7456 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7457 tmp |= LC_SET_QUIESCE; in si_pcie_gen3_enable()
7458 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()
7460 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7461 tmp |= LC_REDO_EQ; in si_pcie_gen3_enable()
7462 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()
7488 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); in si_pcie_gen3_enable()
7489 tmp &= ~LC_SET_QUIESCE; in si_pcie_gen3_enable()
7490 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); in si_pcie_gen3_enable()