793 	u32 tmp = RREG32(CG_CLKPIN_CNTL);  in rv770_get_xclk()  local
795 	if (tmp & MUX_TCLK_TO_XCLK)  in rv770_get_xclk()
798 	if (tmp & XTALIN_DIVIDE)  in rv770_get_xclk()
807 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);  in rv770_page_flip()  local
811 	tmp |= AVIVO_D1GRPH_UPDATE_LOCK;  in rv770_page_flip()
812 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rv770_page_flip()
836 	tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;  in rv770_page_flip()
837 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in rv770_page_flip()
893 	u32 tmp;  in rv770_pcie_gart_enable()  local
910 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |  in rv770_pcie_gart_enable()
914 	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);  in rv770_pcie_gart_enable()
915 	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);  in rv770_pcie_gart_enable()
916 	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);  in rv770_pcie_gart_enable()
918 		WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);  in rv770_pcie_gart_enable()
919 	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);  in rv770_pcie_gart_enable()
920 	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);  in rv770_pcie_gart_enable()
921 	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);  in rv770_pcie_gart_enable()
922 	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);  in rv770_pcie_gart_enable()
943 	u32 tmp;  in rv770_pcie_gart_disable()  local
956 	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);  in rv770_pcie_gart_disable()
957 	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);  in rv770_pcie_gart_disable()
958 	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);  in rv770_pcie_gart_disable()
959 	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);  in rv770_pcie_gart_disable()
960 	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);  in rv770_pcie_gart_disable()
961 	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);  in rv770_pcie_gart_disable()
962 	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);  in rv770_pcie_gart_disable()
963 	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);  in rv770_pcie_gart_disable()
977 	u32 tmp;  in rv770_agp_enable()  local
987 	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |  in rv770_agp_enable()
991 	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);  in rv770_agp_enable()
992 	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);  in rv770_agp_enable()
993 	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);  in rv770_agp_enable()
994 	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);  in rv770_agp_enable()
995 	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);  in rv770_agp_enable()
996 	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);  in rv770_agp_enable()
997 	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);  in rv770_agp_enable()
1005 	u32 tmp;  in rv770_mc_program()  local
1019 	tmp = RREG32(HDP_DEBUG1);  in rv770_mc_program()
1049 	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;  in rv770_mc_program()
1050 	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);  in rv770_mc_program()
1051 	WREG32(MC_VM_FB_LOCATION, tmp);  in rv770_mc_program()
1134 	u32 tmp, i;  in rv770_set_clk_bypass_mode()  local
1139 	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);  in rv770_set_clk_bypass_mode()
1140 	tmp &= SCLK_MUX_SEL_MASK;  in rv770_set_clk_bypass_mode()
1141 	tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;  in rv770_set_clk_bypass_mode()
1142 	WREG32(CG_SPLL_FUNC_CNTL_2, tmp);  in rv770_set_clk_bypass_mode()
1150 	tmp &= ~SCLK_MUX_UPDATE;  in rv770_set_clk_bypass_mode()
1151 	WREG32(CG_SPLL_FUNC_CNTL_2, tmp);  in rv770_set_clk_bypass_mode()
1153 	tmp = RREG32(MPLL_CNTL_MODE);  in rv770_set_clk_bypass_mode()
1155 		tmp &= ~RV730_MPLL_MCLK_SEL;  in rv770_set_clk_bypass_mode()
1157 		tmp &= ~MPLL_MCLK_SEL;  in rv770_set_clk_bypass_mode()
1158 	WREG32(MPLL_CNTL_MODE, tmp);  in rv770_set_clk_bypass_mode()
1182 	u32 db_debug4, tmp;  in rv770_gpu_init()  local
1301 	for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {  in rv770_gpu_init()
1302 		if (!(inactive_pipes & tmp)) {  in rv770_gpu_init()
1305 		tmp <<= 1;  in rv770_gpu_init()
1314 	tmp = rdev->config.rv770.max_simds -  in rv770_gpu_init()
1316 	rdev->config.rv770.active_simds = tmp;  in rv770_gpu_init()
1336 	tmp = 0;  in rv770_gpu_init()
1338 		tmp |= (1 << i);  in rv770_gpu_init()
1340 	if ((disabled_rb_mask & tmp) == tmp) {  in rv770_gpu_init()
1344 	tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;  in rv770_gpu_init()
1345 	tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,  in rv770_gpu_init()
1347 	gb_tiling_config |= tmp << 16;  in rv770_gpu_init()
1348 	rdev->config.rv770.backend_map = tmp;  in rv770_gpu_init()
1641 	u32 tmp;  in rv770_mc_init()  local
1646 	tmp = RREG32(MC_ARB_RAMCFG);  in rv770_mc_init()
1647 	if (tmp & CHANSIZE_OVERRIDE) {  in rv770_mc_init()
1649 	} else if (tmp & CHANSIZE_MASK) {  in rv770_mc_init()
1654 	tmp = RREG32(MC_SHARED_CHMAP);  in rv770_mc_init()
1655 	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {  in rv770_mc_init()
1975 	u32 link_width_cntl, lanes, speed_cntl, tmp;  in rv770_pcie_gen2_enable()  local
2018 		tmp = RREG32(0x541c);  in rv770_pcie_gen2_enable()
2019 		WREG32(0x541c, tmp | 0x8);  in rv770_pcie_gen2_enable()