Lines Matching refs:sclk

440 		state->low.sclk;  in rv6xx_calculate_engine_speed_stepping_parameters()
442 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
444 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1028 rv6xx_calculate_t(state->low.sclk, in rv6xx_calculate_ap()
1029 state->medium.sclk, in rv6xx_calculate_ap()
1036 rv6xx_calculate_t(state->medium.sclk, in rv6xx_calculate_ap()
1037 state->high.sclk, in rv6xx_calculate_ap()
1427 old_state->low.sclk, in rv6xx_generate_transition_stepping()
1428 new_state->low.sclk, in rv6xx_generate_transition_stepping()
1440 new_state->low.sclk, in rv6xx_generate_low_step()
1461 new_state->low.sclk, in rv6xx_generate_stepping_table()
1462 new_state->medium.sclk, in rv6xx_generate_stepping_table()
1466 new_state->medium.sclk, in rv6xx_generate_stepping_table()
1467 new_state->high.sclk, in rv6xx_generate_stepping_table()
1523 if (new_state->high.sclk >= current_state->high.sclk) in rv6xx_set_uvd_clock_before_set_eng_clock()
1540 if (new_state->high.sclk < current_state->high.sclk) in rv6xx_set_uvd_clock_after_set_eng_clock()
1822 u32 sclk, mclk; in rv6xx_parse_pplib_clock_info() local
1839 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); in rv6xx_parse_pplib_clock_info()
1840 sclk |= clock_info->r600.ucEngineClockHigh << 16; in rv6xx_parse_pplib_clock_info()
1845 pl->sclk = sclk; in rv6xx_parse_pplib_clock_info()
1868 pl->sclk = rdev->clock.default_sclk; in rv6xx_parse_pplib_clock_info()
2018 pl->sclk, pl->mclk, pl->vddc); in rv6xx_dpm_print_power_state()
2021 pl->sclk, pl->mclk, pl->vddc); in rv6xx_dpm_print_power_state()
2024 pl->sclk, pl->mclk, pl->vddc); in rv6xx_dpm_print_power_state()
2049 current_index, pl->sclk, pl->mclk, pl->vddc); in rv6xx_dpm_debugfs_print_current_performance_level()
2072 return pl->sclk; in rv6xx_dpm_get_current_sclk()
2115 return requested_state->low.sclk; in rv6xx_dpm_get_sclk()
2117 return requested_state->high.sclk; in rv6xx_dpm_get_sclk()