133 	uint32_t tmp;  in rv515_mc_wait_for_idle()  local
137 		tmp = RREG32_MC(MC_STATUS);  in rv515_mc_wait_for_idle()
138 		if (tmp & MC_STATUS_IDLE) {  in rv515_mc_wait_for_idle()
154 	unsigned pipe_select_current, gb_pipe_select, tmp;  in rv515_gpu_init()  local
163 	tmp = RREG32(R300_DST_PIPE_CONFIG);  in rv515_gpu_init()
164 	pipe_select_current = (tmp >> 2) & 3;  in rv515_gpu_init()
165 	tmp = (1 << pipe_select_current) |  in rv515_gpu_init()
167 	WREG32_PLL(0x000D, tmp);  in rv515_gpu_init()
180 	uint32_t tmp;  in rv515_vram_get_type()  local
184 	tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;  in rv515_vram_get_type()
185 	switch (tmp) {  in rv515_vram_get_type()
241 	uint32_t tmp;  in rv515_debugfs_pipes_info()  local
243 	tmp = RREG32(GB_PIPE_SELECT);  in rv515_debugfs_pipes_info()
244 	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);  in rv515_debugfs_pipes_info()
245 	tmp = RREG32(SU_REG_DEST);  in rv515_debugfs_pipes_info()
246 	seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);  in rv515_debugfs_pipes_info()
247 	tmp = RREG32(GB_TILE_CONFIG);  in rv515_debugfs_pipes_info()
248 	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);  in rv515_debugfs_pipes_info()
249 	tmp = RREG32(DST_PIPE_CONFIG);  in rv515_debugfs_pipes_info()
250 	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);  in rv515_debugfs_pipes_info()
259 	uint32_t tmp;  in rv515_debugfs_ga_info()  local
261 	tmp = RREG32(0x2140);  in rv515_debugfs_ga_info()
262 	seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);  in rv515_debugfs_ga_info()
264 	tmp = RREG32(0x425C);  in rv515_debugfs_ga_info()
265 	seq_printf(m, "GA_IDLE 0x%08x\n", tmp);  in rv515_debugfs_ga_info()
298 	u32 crtc_enabled, tmp, frame_count, blackout;  in rv515_mc_stop()  local
311 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
312 			if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {  in rv515_mc_stop()
315 				tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;  in rv515_mc_stop()
316 				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
329 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
330 			tmp &= ~AVIVO_CRTC_EN;  in rv515_mc_stop()
331 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
364 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_stop()
365 			if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {  in rv515_mc_stop()
366 				tmp |= AVIVO_D1GRPH_UPDATE_LOCK;  in rv515_mc_stop()
367 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_stop()
369 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_stop()
370 			if (!(tmp & 1)) {  in rv515_mc_stop()
371 				tmp |= 1;  in rv515_mc_stop()
372 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_stop()
380 	u32 tmp, frame_count;  in rv515_mc_resume()  local
408 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);  in rv515_mc_resume()
409 			if ((tmp & 0x7) != 3) {  in rv515_mc_resume()
410 				tmp &= ~0x7;  in rv515_mc_resume()
411 				tmp |= 0x3;  in rv515_mc_resume()
412 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);  in rv515_mc_resume()
414 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
415 			if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {  in rv515_mc_resume()
416 				tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;  in rv515_mc_resume()
417 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_resume()
419 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_resume()
420 			if (tmp & 1) {  in rv515_mc_resume()
421 				tmp &= ~1;  in rv515_mc_resume()
422 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_resume()
425 				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
426 				if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)  in rv515_mc_resume()
436 			tmp = RREG32(R700_MC_CITF_CNTL);  in rv515_mc_resume()
438 			tmp = RREG32(R600_CITF_CNTL);  in rv515_mc_resume()
439 		tmp &= ~R600_BLACKOUT_MASK;  in rv515_mc_resume()
441 			WREG32(R700_MC_CITF_CNTL, tmp);  in rv515_mc_resume()
443 			WREG32(R600_CITF_CNTL, tmp);  in rv515_mc_resume()
450 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_resume()
451 			tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;  in rv515_mc_resume()
452 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_resume()
1239 	u32 tmp;  in rv515_bandwidth_avivo_update()  local
1255 	tmp = wm0_high.lb_request_fifo_depth;  in rv515_bandwidth_avivo_update()
1256 	tmp |= wm1_high.lb_request_fifo_depth << 16;  in rv515_bandwidth_avivo_update()
1257 	WREG32(LB_MAX_REQ_OUTSTANDING, tmp);  in rv515_bandwidth_avivo_update()
1276 	uint32_t tmp;  in rv515_bandwidth_update()  local
1296 		tmp = RREG32_MC(MC_MISC_LAT_TIMER);  in rv515_bandwidth_update()
1297 		tmp &= ~MC_DISP1R_INIT_LAT_MASK;  in rv515_bandwidth_update()
1298 		tmp &= ~MC_DISP0R_INIT_LAT_MASK;  in rv515_bandwidth_update()
1300 			tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);  in rv515_bandwidth_update()
1302 			tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);  in rv515_bandwidth_update()
1303 		WREG32_MC(MC_MISC_LAT_TIMER, tmp);  in rv515_bandwidth_update()