240 	uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);  in radeon_vm_flush()
362 				uint64_t pe,  in radeon_vm_set_pages()
363 				uint64_t addr, unsigned count,  in radeon_vm_set_pages()
369 		uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;  in radeon_vm_set_pages()
393 	uint64_t addr;  in radeon_vm_clear_bo()
448 			  uint64_t soffset,  in radeon_vm_bo_set_addr()
451 	uint64_t size = radeon_bo_size(bo_va->bo);  in radeon_vm_bo_set_addr()
454 	uint64_t eoffset;  in radeon_vm_bo_set_addr()
597 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)  in radeon_vm_map_gart()
599 	uint64_t result;  in radeon_vm_map_gart()
646 	uint64_t pd_addr = radeon_bo_gpu_offset(pd);  in radeon_vm_update_page_directory()
648 	uint64_t last_pde = ~0, last_pt = ~0;  in radeon_vm_update_page_directory()
671 		uint64_t pde, pt;  in radeon_vm_update_page_directory()
735 				uint64_t pe_start, uint64_t pe_end,  in radeon_vm_frag_ptes()
736 				uint64_t addr, uint32_t flags)  in radeon_vm_frag_ptes()
758 	uint64_t frag_flags = ((rdev->family == CHIP_CAYMAN) ||  in radeon_vm_frag_ptes()
761 	uint64_t frag_align = ((rdev->family == CHIP_CAYMAN) ||  in radeon_vm_frag_ptes()
764 	uint64_t frag_start = ALIGN(pe_start, frag_align);  in radeon_vm_frag_ptes()
765 	uint64_t frag_end = pe_end & ~(frag_align - 1);  in radeon_vm_frag_ptes()
818 				 uint64_t start, uint64_t end,  in radeon_vm_update_ptes()
819 				 uint64_t dst, uint32_t flags)  in radeon_vm_update_ptes()
821 	uint64_t mask = RADEON_VM_PTE_COUNT - 1;  in radeon_vm_update_ptes()
822 	uint64_t last_pte = ~0, last_dst = ~0;  in radeon_vm_update_ptes()
824 	uint64_t addr;  in radeon_vm_update_ptes()
828 		uint64_t pt_idx = addr >> radeon_vm_block_size;  in radeon_vm_update_ptes()
831 		uint64_t pte;  in radeon_vm_update_ptes()
888 				uint64_t start, uint64_t end,  in radeon_vm_fence_pts()
920 	uint64_t addr;  in radeon_vm_bo_update()