470 			     drm_radeon_texture_regs_t * tex,  in radeon_emit_state()  argument
573 						  &tex[0].pp_txoffset)) {  in radeon_emit_state()
580 		OUT_RING(tex[0].pp_txfilter);  in radeon_emit_state()
581 		OUT_RING(tex[0].pp_txformat);  in radeon_emit_state()
582 		OUT_RING(tex[0].pp_txoffset);  in radeon_emit_state()
583 		OUT_RING(tex[0].pp_txcblend);  in radeon_emit_state()
584 		OUT_RING(tex[0].pp_txablend);  in radeon_emit_state()
585 		OUT_RING(tex[0].pp_tfactor);  in radeon_emit_state()
587 		OUT_RING(tex[0].pp_border_color);  in radeon_emit_state()
593 						  &tex[1].pp_txoffset)) {  in radeon_emit_state()
600 		OUT_RING(tex[1].pp_txfilter);  in radeon_emit_state()
601 		OUT_RING(tex[1].pp_txformat);  in radeon_emit_state()
602 		OUT_RING(tex[1].pp_txoffset);  in radeon_emit_state()
603 		OUT_RING(tex[1].pp_txcblend);  in radeon_emit_state()
604 		OUT_RING(tex[1].pp_txablend);  in radeon_emit_state()
605 		OUT_RING(tex[1].pp_tfactor);  in radeon_emit_state()
607 		OUT_RING(tex[1].pp_border_color);  in radeon_emit_state()
613 						  &tex[2].pp_txoffset)) {  in radeon_emit_state()
620 		OUT_RING(tex[2].pp_txfilter);  in radeon_emit_state()
621 		OUT_RING(tex[2].pp_txformat);  in radeon_emit_state()
622 		OUT_RING(tex[2].pp_txoffset);  in radeon_emit_state()
623 		OUT_RING(tex[2].pp_txcblend);  in radeon_emit_state()
624 		OUT_RING(tex[2].pp_txablend);  in radeon_emit_state()
625 		OUT_RING(tex[2].pp_tfactor);  in radeon_emit_state()
627 		OUT_RING(tex[2].pp_border_color);  in radeon_emit_state()
651 				 state->tex, state->dirty);  in radeon_emit_state2()
1698 				      drm_radeon_texture_t * tex,  in radeon_cp_dispatch_texture()  argument
1713 	if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {  in radeon_cp_dispatch_texture()
1733 	switch (tex->format) {  in radeon_cp_dispatch_texture()
1737 		tex_width = tex->width * 4;  in radeon_cp_dispatch_texture()
1747 		tex_width = tex->width * 2;  in radeon_cp_dispatch_texture()
1753 		tex_width = tex->width * 1;  in radeon_cp_dispatch_texture()
1757 		DRM_ERROR("invalid texture format %d\n", tex->format);  in radeon_cp_dispatch_texture()
1764 	texpitch = tex->pitch;  in radeon_cp_dispatch_texture()
1776 	if (!radeon_check_offset(dev_priv, tex->offset + image->height *  in radeon_cp_dispatch_texture()
1782 	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);  in radeon_cp_dispatch_texture()
1786 			  tex->offset >> 10, tex->pitch, tex->format,  in radeon_cp_dispatch_texture()
1813 			if (copy_to_user(tex->image, image, sizeof(*image)))  in radeon_cp_dispatch_texture()
1841 			if (tex->height == 1) {  in radeon_cp_dispatch_texture()
1854 				for (i = 0; i < tex->height; i++) {  in radeon_cp_dispatch_texture()
1862 				for (i = 0; i < tex->height; i += 2) {  in radeon_cp_dispatch_texture()
1886 				for (i = 0; i < tex->height; i++) {  in radeon_cp_dispatch_texture()
1910 		OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));  in radeon_cp_dispatch_texture()
2428 	drm_radeon_texture_t *tex = data;  in radeon_cp_texture()  local
2434 	if (tex->image == NULL) {  in radeon_cp_texture()
2440 			       (drm_radeon_tex_image_t __user *) tex->image,  in radeon_cp_texture()
2448 		ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);  in radeon_cp_texture()
2450 		ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);  in radeon_cp_texture()