341 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
342 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
344 #define GET_RING_HEAD(dev_priv)	radeon_get_ring_head(dev_priv)  argument
345 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)  argument
350 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,  in radeon_check_offset()  argument
353 	u32 fb_start = dev_priv->fb_location;  in radeon_check_offset()
354 	u32 fb_end = fb_start + dev_priv->fb_size - 1;  in radeon_check_offset()
355 	u32 gart_start = dev_priv->gart_vm_start;  in radeon_check_offset()
356 	u32 gart_end = gart_start + dev_priv->gart_size - 1;  in radeon_check_offset()
375 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
376 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
377 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
382 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
384 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
397 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
398 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
399 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
447 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
448 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
449 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
450 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
740 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
742 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)  argument
1848 #define RADEON_READ(reg)	DRM_READ32(  dev_priv->mmio, (reg) )
1852 		DRM_WRITE32(dev_priv->mmio, (reg), (val));		\
1854 		DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg));	\
1855 		DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val));	\
1858 #define RADEON_READ8(reg)	DRM_READ8(  dev_priv->mmio, (reg) )
1859 #define RADEON_WRITE8(reg,val)	DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1905 	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||   \
1906 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))      \
1908 	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)  \
1954 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
1964 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
1974 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
1984 	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
1999 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\  argument
2001 	if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) {		\
2002 		u32 head = GET_RING_HEAD( dev_priv );			\
2003 		if (head == dev_priv->ring.tail)			\
2004 			dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE;	\
2008 #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\  argument
2014 		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2015 			__ret = r600_do_cp_idle(dev_priv);		\
2017 			__ret = radeon_do_cp_idle(dev_priv);		\
2071 	_align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1));	\
2073 	if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) {	\
2075 		radeon_wait_ring( dev_priv, _align_nr * sizeof(u32));	\
2077 	_nr = n; dev_priv->ring.space -= (n) * sizeof(u32);		\
2078 	ring = dev_priv->ring.start;					\
2079 	write = dev_priv->ring.tail;					\
2080 	mask = dev_priv->ring.tail_mask;				\
2086 			  write, dev_priv->ring.tail );			\
2088 	if (((dev_priv->ring.tail + _nr) & mask) != write) {		\
2091 			((dev_priv->ring.tail + _nr) & mask),		\
2094 		dev_priv->ring.tail = write;				\
2097 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2100 		radeon_commit_ring(dev_priv);				\