Lines Matching refs:dev_priv
61 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
63 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) in radeon_read_ring_rptr() argument
67 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_read_ring_rptr()
68 val = DRM_READ32(dev_priv->ring_rptr, off); in radeon_read_ring_rptr()
71 dev_priv->ring_rptr->handle) + in radeon_read_ring_rptr()
78 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) in radeon_get_ring_head() argument
80 if (dev_priv->writeback_works) in radeon_get_ring_head()
81 return radeon_read_ring_rptr(dev_priv, 0); in radeon_get_ring_head()
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_ring_head()
90 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) in radeon_write_ring_rptr() argument
92 if (dev_priv->flags & RADEON_IS_AGP) in radeon_write_ring_rptr()
93 DRM_WRITE32(dev_priv->ring_rptr, off, val); in radeon_write_ring_rptr()
95 *(((volatile u32 *) dev_priv->ring_rptr->handle) + in radeon_write_ring_rptr()
99 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) in radeon_set_ring_head() argument
101 radeon_write_ring_rptr(dev_priv, 0, val); in radeon_set_ring_head()
104 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) in radeon_get_scratch() argument
106 if (dev_priv->writeback_works) { in radeon_get_scratch()
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_scratch()
108 return radeon_read_ring_rptr(dev_priv, in radeon_get_scratch()
111 return radeon_read_ring_rptr(dev_priv, in radeon_get_scratch()
114 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_scratch()
121 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in R500_READ_MCIND() argument
130 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS480_READ_MCIND() argument
139 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS690_READ_MCIND() argument
148 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS600_READ_MCIND() argument
157 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in IGP_READ_MCIND() argument
159 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in IGP_READ_MCIND()
160 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in IGP_READ_MCIND()
161 return RS690_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in IGP_READ_MCIND()
163 return RS600_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
165 return RS480_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
168 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) in radeon_read_fb_location() argument
171 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_read_fb_location()
173 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_read_fb_location()
175 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_read_fb_location()
176 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); in radeon_read_fb_location()
177 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_read_fb_location()
178 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_read_fb_location()
179 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); in radeon_read_fb_location()
180 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_read_fb_location()
181 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); in radeon_read_fb_location()
182 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_read_fb_location()
183 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); in radeon_read_fb_location()
188 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) in radeon_write_fb_location() argument
190 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_write_fb_location()
192 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_write_fb_location()
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_write_fb_location()
196 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_fb_location()
197 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_write_fb_location()
199 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_write_fb_location()
201 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_write_fb_location()
207 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) in radeon_write_agp_location() argument
210 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { in radeon_write_agp_location()
213 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_write_agp_location()
216 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_write_agp_location()
218 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_agp_location()
219 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_write_agp_location()
221 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_write_agp_location()
223 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_write_agp_location()
229 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) in radeon_write_agp_base() argument
236 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_write_agp_base()
238 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_write_agp_base()
240 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { in radeon_write_agp_base()
243 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_agp_base()
244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { in radeon_write_agp_base()
247 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { in radeon_write_agp_base()
250 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { in radeon_write_agp_base()
253 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || in radeon_write_agp_base()
254 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { in radeon_write_agp_base()
259 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) in radeon_write_agp_base()
264 void radeon_enable_bm(struct drm_radeon_private *dev_priv) in radeon_enable_bm() argument
268 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_enable_bm()
269 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { in radeon_enable_bm()
273 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || in radeon_enable_bm()
274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || in radeon_enable_bm()
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || in radeon_enable_bm()
276 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { in radeon_enable_bm()
285 drm_radeon_private_t *dev_priv = dev->dev_private; in RADEON_READ_PLL() local
291 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_PCIE() argument
298 static void radeon_status(drm_radeon_private_t * dev_priv) in radeon_status() argument
324 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) in radeon_do_pixcache_flush() argument
329 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_pixcache_flush()
331 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { in radeon_do_pixcache_flush()
336 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_pixcache_flush()
350 radeon_status(dev_priv); in radeon_do_pixcache_flush()
355 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) in radeon_do_wait_for_fifo() argument
359 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_wait_for_fifo()
361 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_fifo()
374 radeon_status(dev_priv); in radeon_do_wait_for_fifo()
379 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) in radeon_do_wait_for_idle() argument
383 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_wait_for_idle()
385 ret = radeon_do_wait_for_fifo(dev_priv, 64); in radeon_do_wait_for_idle()
389 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_idle()
392 radeon_do_pixcache_flush(dev_priv); in radeon_do_wait_for_idle()
403 radeon_status(dev_priv); in radeon_do_wait_for_idle()
410 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_init_pipes() local
413 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { in radeon_init_pipes()
416 dev_priv->num_z_pipes = 2; in radeon_init_pipes()
418 dev_priv->num_z_pipes = 1; in radeon_init_pipes()
420 dev_priv->num_z_pipes = 1; in radeon_init_pipes()
423 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { in radeon_init_pipes()
425 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; in radeon_init_pipes()
429 dev_priv->num_gb_pipes = 1; in radeon_init_pipes()
432 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 && in radeon_init_pipes()
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 && in radeon_init_pipes()
436 dev_priv->num_gb_pipes = 2; in radeon_init_pipes()
439 dev_priv->num_gb_pipes = 1; in radeon_init_pipes()
442 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); in radeon_init_pipes()
446 switch (dev_priv->num_gb_pipes) { in radeon_init_pipes()
454 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { in radeon_init_pipes()
456 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); in radeon_init_pipes()
459 radeon_do_wait_for_idle(dev_priv); in radeon_init_pipes()
473 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv) in radeon_cp_init_microcode() argument
488 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || in radeon_cp_init_microcode()
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || in radeon_cp_init_microcode()
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || in radeon_cp_init_microcode()
491 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || in radeon_cp_init_microcode()
492 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { in radeon_cp_init_microcode()
495 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || in radeon_cp_init_microcode()
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || in radeon_cp_init_microcode()
497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || in radeon_cp_init_microcode()
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { in radeon_cp_init_microcode()
501 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || in radeon_cp_init_microcode()
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || in radeon_cp_init_microcode()
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || in radeon_cp_init_microcode()
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || in radeon_cp_init_microcode()
505 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || in radeon_cp_init_microcode()
506 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { in radeon_cp_init_microcode()
509 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || in radeon_cp_init_microcode()
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || in radeon_cp_init_microcode()
511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { in radeon_cp_init_microcode()
514 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_cp_init_microcode()
515 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { in radeon_cp_init_microcode()
518 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { in radeon_cp_init_microcode()
521 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || in radeon_cp_init_microcode()
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || in radeon_cp_init_microcode()
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || in radeon_cp_init_microcode()
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || in radeon_cp_init_microcode()
525 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || in radeon_cp_init_microcode()
526 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { in radeon_cp_init_microcode()
531 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); in radeon_cp_init_microcode()
536 } else if (dev_priv->me_fw->size % 8) { in radeon_cp_init_microcode()
539 dev_priv->me_fw->size, fw_name); in radeon_cp_init_microcode()
541 release_firmware(dev_priv->me_fw); in radeon_cp_init_microcode()
542 dev_priv->me_fw = NULL; in radeon_cp_init_microcode()
547 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) in radeon_cp_load_microcode() argument
552 radeon_do_wait_for_idle(dev_priv); in radeon_cp_load_microcode()
554 if (dev_priv->me_fw) { in radeon_cp_load_microcode()
555 size = dev_priv->me_fw->size / 4; in radeon_cp_load_microcode()
556 fw_data = (const __be32 *)&dev_priv->me_fw->data[0]; in radeon_cp_load_microcode()
571 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) in radeon_do_cp_flush() argument
584 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) in radeon_do_cp_idle() argument
598 return radeon_do_wait_for_idle(dev_priv); in radeon_do_cp_idle()
603 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) in radeon_do_cp_start() argument
608 radeon_do_wait_for_idle(dev_priv); in radeon_do_cp_start()
610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()
612 dev_priv->cp_running = 1; in radeon_do_cp_start()
617 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { in radeon_do_cp_start()
639 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; in radeon_do_cp_start()
646 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) in radeon_do_cp_reset() argument
653 SET_RING_HEAD(dev_priv, cur_read_ptr); in radeon_do_cp_reset()
654 dev_priv->ring.tail = cur_read_ptr; in radeon_do_cp_reset()
661 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) in radeon_do_cp_stop() argument
667 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) { in radeon_do_cp_stop()
673 radeon_do_wait_for_idle(dev_priv); in radeon_do_cp_stop()
678 dev_priv->cp_running = 0; in radeon_do_cp_stop()
685 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_engine_reset() local
689 radeon_do_pixcache_flush(dev_priv); in radeon_do_engine_reset()
691 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { in radeon_do_engine_reset()
726 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { in radeon_do_engine_reset()
733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) in radeon_do_engine_reset()
737 radeon_do_cp_reset(dev_priv); in radeon_do_engine_reset()
740 dev_priv->cp_running = 0; in radeon_do_engine_reset()
749 drm_radeon_private_t *dev_priv, in radeon_cp_init_ring_buffer() argument
760 if (!dev_priv->new_memmap) in radeon_cp_init_ring_buffer()
761 radeon_write_fb_location(dev_priv, in radeon_cp_init_ring_buffer()
762 ((dev_priv->gart_vm_start - 1) & 0xffff0000) in radeon_cp_init_ring_buffer()
763 | (dev_priv->fb_location >> 16)); in radeon_cp_init_ring_buffer()
766 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_cp_init_ring_buffer()
767 radeon_write_agp_base(dev_priv, dev->agp->base); in radeon_cp_init_ring_buffer()
769 radeon_write_agp_location(dev_priv, in radeon_cp_init_ring_buffer()
770 (((dev_priv->gart_vm_start - 1 + in radeon_cp_init_ring_buffer()
771 dev_priv->gart_size) & 0xffff0000) | in radeon_cp_init_ring_buffer()
772 (dev_priv->gart_vm_start >> 16))); in radeon_cp_init_ring_buffer()
774 ring_start = (dev_priv->cp_ring->offset in radeon_cp_init_ring_buffer()
776 + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
779 ring_start = (dev_priv->cp_ring->offset in radeon_cp_init_ring_buffer()
781 + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
791 SET_RING_HEAD(dev_priv, cur_read_ptr); in radeon_cp_init_ring_buffer()
792 dev_priv->ring.tail = cur_read_ptr; in radeon_cp_init_ring_buffer()
795 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_cp_init_ring_buffer()
797 dev_priv->ring_rptr->offset in radeon_cp_init_ring_buffer()
798 - dev->agp->base + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
803 dev_priv->ring_rptr->offset in radeon_cp_init_ring_buffer()
805 + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
812 (dev_priv->ring.fetch_size_l2ow << 18) | in radeon_cp_init_ring_buffer()
813 (dev_priv->ring.rptr_update_l2qw << 8) | in radeon_cp_init_ring_buffer()
814 dev_priv->ring.size_l2qw); in radeon_cp_init_ring_buffer()
817 (dev_priv->ring.fetch_size_l2ow << 18) | in radeon_cp_init_ring_buffer()
818 (dev_priv->ring.rptr_update_l2qw << 8) | in radeon_cp_init_ring_buffer()
819 dev_priv->ring.size_l2qw); in radeon_cp_init_ring_buffer()
835 radeon_enable_bm(dev_priv); in radeon_cp_init_ring_buffer()
837 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); in radeon_cp_init_ring_buffer()
840 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); in radeon_cp_init_ring_buffer()
843 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); in radeon_cp_init_ring_buffer()
854 radeon_do_wait_for_idle(dev_priv); in radeon_cp_init_ring_buffer()
865 static void radeon_test_writeback(drm_radeon_private_t * dev_priv) in radeon_test_writeback() argument
870 dev_priv->writeback_works = 0; in radeon_test_writeback()
875 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); in radeon_test_writeback()
879 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { in radeon_test_writeback()
882 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); in radeon_test_writeback()
888 if (tmp < dev_priv->usec_timeout) { in radeon_test_writeback()
889 dev_priv->writeback_works = 1; in radeon_test_writeback()
892 dev_priv->writeback_works = 0; in radeon_test_writeback()
896 dev_priv->writeback_works = 0; in radeon_test_writeback()
900 if (!dev_priv->writeback_works) { in radeon_test_writeback()
909 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) in radeon_set_igpgart() argument
915 dev_priv->gart_vm_start, in radeon_set_igpgart()
916 (long)dev_priv->gart_info.bus_addr, in radeon_set_igpgart()
917 dev_priv->gart_size); in radeon_set_igpgart()
919 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); in radeon_set_igpgart()
920 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_set_igpgart()
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_set_igpgart()
930 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); in radeon_set_igpgart()
936 temp = dev_priv->gart_info.bus_addr & 0xfffff000; in radeon_set_igpgart()
937 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; in radeon_set_igpgart()
940 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); in radeon_set_igpgart()
944 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); in radeon_set_igpgart()
946 dev_priv->gart_size = 32*1024*1024; in radeon_set_igpgart()
947 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & in radeon_set_igpgart()
948 0xffff0000) | (dev_priv->gart_vm_start >> 16)); in radeon_set_igpgart()
950 radeon_write_agp_location(dev_priv, temp); in radeon_set_igpgart()
952 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); in radeon_set_igpgart()
957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()
967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()
980 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) in rs600_set_igpgart() argument
987 dev_priv->gart_vm_start, in rs600_set_igpgart()
988 (long)dev_priv->gart_info.bus_addr, in rs600_set_igpgart()
989 dev_priv->gart_size); in rs600_set_igpgart()
1012 dev_priv->gart_info.bus_addr); in rs600_set_igpgart()
1014 dev_priv->gart_vm_start); in rs600_set_igpgart()
1016 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
1021 dev_priv->gart_vm_start); in rs600_set_igpgart()
1023 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
1026 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
1029 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); in rs600_set_igpgart()
1033 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
1037 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
1041 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
1045 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
1049 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); in rs600_set_igpgart()
1055 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) in radeon_set_pciegart() argument
1057 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); in radeon_set_pciegart()
1061 dev_priv->gart_vm_start, in radeon_set_pciegart()
1062 (long)dev_priv->gart_info.bus_addr, in radeon_set_pciegart()
1063 dev_priv->gart_size); in radeon_set_pciegart()
1065 dev_priv->gart_vm_start); in radeon_set_pciegart()
1067 dev_priv->gart_info.bus_addr); in radeon_set_pciegart()
1069 dev_priv->gart_vm_start); in radeon_set_pciegart()
1071 dev_priv->gart_vm_start + in radeon_set_pciegart()
1072 dev_priv->gart_size - 1); in radeon_set_pciegart()
1074 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ in radeon_set_pciegart()
1085 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) in radeon_set_pcigart() argument
1089 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_set_pcigart()
1090 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || in radeon_set_pcigart()
1091 (dev_priv->flags & RADEON_IS_IGPGART)) { in radeon_set_pcigart()
1092 radeon_set_igpgart(dev_priv, on); in radeon_set_pcigart()
1096 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { in radeon_set_pcigart()
1097 rs600_set_igpgart(dev_priv, on); in radeon_set_pcigart()
1101 if (dev_priv->flags & RADEON_IS_PCIE) { in radeon_set_pcigart()
1102 radeon_set_pciegart(dev_priv, on); in radeon_set_pcigart()
1114 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); in radeon_set_pcigart()
1118 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); in radeon_set_pcigart()
1119 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start in radeon_set_pcigart()
1120 + dev_priv->gart_size - 1); in radeon_set_pcigart()
1124 radeon_write_agp_location(dev_priv, 0xffffffc0); in radeon_set_pcigart()
1132 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) in radeon_setup_pcigart_surface() argument
1134 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; in radeon_setup_pcigart_surface()
1139 if (!dev_priv->virt_surfaces[i].file_priv || in radeon_setup_pcigart_surface()
1140 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) in radeon_setup_pcigart_surface()
1145 vp = &dev_priv->virt_surfaces[i]; in radeon_setup_pcigart_surface()
1148 struct radeon_surface *sp = &dev_priv->surfaces[i]; in radeon_setup_pcigart_surface()
1175 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_init_cp() local
1181 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { in radeon_do_init_cp()
1187 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { in radeon_do_init_cp()
1189 dev_priv->flags &= ~RADEON_IS_AGP; in radeon_do_init_cp()
1190 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) in radeon_do_init_cp()
1193 dev_priv->flags |= RADEON_IS_AGP; in radeon_do_init_cp()
1196 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { in radeon_do_init_cp()
1202 dev_priv->usec_timeout = init->usec_timeout; in radeon_do_init_cp()
1203 if (dev_priv->usec_timeout < 1 || in radeon_do_init_cp()
1204 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { in radeon_do_init_cp()
1212 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; in radeon_do_init_cp()
1216 dev_priv->microcode_version = UCODE_R200; in radeon_do_init_cp()
1219 dev_priv->microcode_version = UCODE_R300; in radeon_do_init_cp()
1222 dev_priv->microcode_version = UCODE_R100; in radeon_do_init_cp()
1225 dev_priv->do_boxes = 0; in radeon_do_init_cp()
1226 dev_priv->cp_mode = init->cp_mode; in radeon_do_init_cp()
1241 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; in radeon_do_init_cp()
1245 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; in radeon_do_init_cp()
1248 dev_priv->front_offset = init->front_offset; in radeon_do_init_cp()
1249 dev_priv->front_pitch = init->front_pitch; in radeon_do_init_cp()
1250 dev_priv->back_offset = init->back_offset; in radeon_do_init_cp()
1251 dev_priv->back_pitch = init->back_pitch; in radeon_do_init_cp()
1255 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; in radeon_do_init_cp()
1259 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; in radeon_do_init_cp()
1262 dev_priv->depth_offset = init->depth_offset; in radeon_do_init_cp()
1263 dev_priv->depth_pitch = init->depth_pitch; in radeon_do_init_cp()
1270 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | in radeon_do_init_cp()
1271 (dev_priv->color_fmt << 10) | in radeon_do_init_cp()
1272 (dev_priv->microcode_version == in radeon_do_init_cp()
1275 dev_priv->depth_clear.rb3d_zstencilcntl = in radeon_do_init_cp()
1276 (dev_priv->depth_fmt | in radeon_do_init_cp()
1283 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | in radeon_do_init_cp()
1296 dev_priv->ring_offset = init->ring_offset; in radeon_do_init_cp()
1297 dev_priv->ring_rptr_offset = init->ring_rptr_offset; in radeon_do_init_cp()
1298 dev_priv->buffers_offset = init->buffers_offset; in radeon_do_init_cp()
1299 dev_priv->gart_textures_offset = init->gart_textures_offset; in radeon_do_init_cp()
1308 dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset); in radeon_do_init_cp()
1309 if (!dev_priv->cp_ring) { in radeon_do_init_cp()
1314 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset); in radeon_do_init_cp()
1315 if (!dev_priv->ring_rptr) { in radeon_do_init_cp()
1329 dev_priv->gart_textures = in radeon_do_init_cp()
1331 if (!dev_priv->gart_textures) { in radeon_do_init_cp()
1339 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1340 drm_legacy_ioremap_wc(dev_priv->cp_ring, dev); in radeon_do_init_cp()
1341 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); in radeon_do_init_cp()
1343 if (!dev_priv->cp_ring->handle || in radeon_do_init_cp()
1344 !dev_priv->ring_rptr->handle || in radeon_do_init_cp()
1353 dev_priv->cp_ring->handle = in radeon_do_init_cp()
1354 (void *)(unsigned long)dev_priv->cp_ring->offset; in radeon_do_init_cp()
1355 dev_priv->ring_rptr->handle = in radeon_do_init_cp()
1356 (void *)(unsigned long)dev_priv->ring_rptr->offset; in radeon_do_init_cp()
1361 dev_priv->cp_ring->handle); in radeon_do_init_cp()
1363 dev_priv->ring_rptr->handle); in radeon_do_init_cp()
1368 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; in radeon_do_init_cp()
1369 dev_priv->fb_size = in radeon_do_init_cp()
1370 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) in radeon_do_init_cp()
1371 - dev_priv->fb_location; in radeon_do_init_cp()
1373 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | in radeon_do_init_cp()
1374 ((dev_priv->front_offset in radeon_do_init_cp()
1375 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1377 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | in radeon_do_init_cp()
1378 ((dev_priv->back_offset in radeon_do_init_cp()
1379 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1381 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | in radeon_do_init_cp()
1382 ((dev_priv->depth_offset in radeon_do_init_cp()
1383 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1385 dev_priv->gart_size = init->gart_size; in radeon_do_init_cp()
1388 if (dev_priv->new_memmap) { in radeon_do_init_cp()
1398 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1401 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in radeon_do_init_cp()
1402 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { in radeon_do_init_cp()
1411 base = dev_priv->fb_location + dev_priv->fb_size; in radeon_do_init_cp()
1412 if (base < dev_priv->fb_location || in radeon_do_init_cp()
1413 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in radeon_do_init_cp()
1414 base = dev_priv->fb_location in radeon_do_init_cp()
1415 - dev_priv->gart_size; in radeon_do_init_cp()
1417 dev_priv->gart_vm_start = base & 0xffc00000u; in radeon_do_init_cp()
1418 if (dev_priv->gart_vm_start != base) in radeon_do_init_cp()
1420 base, dev_priv->gart_vm_start); in radeon_do_init_cp()
1423 dev_priv->gart_vm_start = dev_priv->fb_location + in radeon_do_init_cp()
1428 if (dev_priv->flags & RADEON_IS_AGP) in radeon_do_init_cp()
1429 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in radeon_do_init_cp()
1431 + dev_priv->gart_vm_start); in radeon_do_init_cp()
1434 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in radeon_do_init_cp()
1436 + dev_priv->gart_vm_start); in radeon_do_init_cp()
1438 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); in radeon_do_init_cp()
1439 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); in radeon_do_init_cp()
1441 dev_priv->gart_buffers_offset); in radeon_do_init_cp()
1443 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; in radeon_do_init_cp()
1444 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle in radeon_do_init_cp()
1446 dev_priv->ring.size = init->ring_size; in radeon_do_init_cp()
1447 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8); in radeon_do_init_cp()
1449 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; in radeon_do_init_cp()
1450 dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8); in radeon_do_init_cp()
1452 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; in radeon_do_init_cp()
1453 dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16); in radeon_do_init_cp()
1454 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in radeon_do_init_cp()
1456 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; in radeon_do_init_cp()
1459 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1461 radeon_set_pcigart(dev_priv, 0); in radeon_do_init_cp()
1468 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); in radeon_do_init_cp()
1470 if (dev_priv->pcigart_offset_set) { in radeon_do_init_cp()
1471 dev_priv->gart_info.bus_addr = in radeon_do_init_cp()
1472 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location; in radeon_do_init_cp()
1473 dev_priv->gart_info.mapping.offset = in radeon_do_init_cp()
1474 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in radeon_do_init_cp()
1475 dev_priv->gart_info.mapping.size = in radeon_do_init_cp()
1476 dev_priv->gart_info.table_size; in radeon_do_init_cp()
1478 drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev); in radeon_do_init_cp()
1479 dev_priv->gart_info.addr = in radeon_do_init_cp()
1480 dev_priv->gart_info.mapping.handle; in radeon_do_init_cp()
1482 if (dev_priv->flags & RADEON_IS_PCIE) in radeon_do_init_cp()
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; in radeon_do_init_cp()
1485 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; in radeon_do_init_cp()
1486 dev_priv->gart_info.gart_table_location = in radeon_do_init_cp()
1490 dev_priv->gart_info.addr, in radeon_do_init_cp()
1491 dev_priv->pcigart_offset); in radeon_do_init_cp()
1493 if (dev_priv->flags & RADEON_IS_IGPGART) in radeon_do_init_cp()
1494 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; in radeon_do_init_cp()
1496 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; in radeon_do_init_cp()
1497 dev_priv->gart_info.gart_table_location = in radeon_do_init_cp()
1499 dev_priv->gart_info.addr = NULL; in radeon_do_init_cp()
1500 dev_priv->gart_info.bus_addr = 0; in radeon_do_init_cp()
1501 if (dev_priv->flags & RADEON_IS_PCIE) { in radeon_do_init_cp()
1511 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_init_cp()
1514 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1523 ret = radeon_setup_pcigart_surface(dev_priv); in radeon_do_init_cp()
1526 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_init_cp()
1527 r600_page_table_cleanup(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1529 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1535 radeon_set_pcigart(dev_priv, 1); in radeon_do_init_cp()
1538 if (!dev_priv->me_fw) { in radeon_do_init_cp()
1539 int err = radeon_cp_init_microcode(dev_priv); in radeon_do_init_cp()
1546 radeon_cp_load_microcode(dev_priv); in radeon_do_init_cp()
1547 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); in radeon_do_init_cp()
1549 dev_priv->last_buf = 0; in radeon_do_init_cp()
1552 radeon_test_writeback(dev_priv); in radeon_do_init_cp()
1559 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_cleanup_cp() local
1570 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_cleanup_cp()
1571 if (dev_priv->cp_ring != NULL) { in radeon_do_cleanup_cp()
1572 drm_legacy_ioremapfree(dev_priv->cp_ring, dev); in radeon_do_cleanup_cp()
1573 dev_priv->cp_ring = NULL; in radeon_do_cleanup_cp()
1575 if (dev_priv->ring_rptr != NULL) { in radeon_do_cleanup_cp()
1576 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev); in radeon_do_cleanup_cp()
1577 dev_priv->ring_rptr = NULL; in radeon_do_cleanup_cp()
1587 if (dev_priv->gart_info.bus_addr) { in radeon_do_cleanup_cp()
1589 radeon_set_pcigart(dev_priv, 0); in radeon_do_cleanup_cp()
1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_cleanup_cp()
1591 r600_page_table_cleanup(dev, &dev_priv->gart_info); in radeon_do_cleanup_cp()
1593 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) in radeon_do_cleanup_cp()
1598 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) in radeon_do_cleanup_cp()
1600 drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev); in radeon_do_cleanup_cp()
1601 dev_priv->gart_info.addr = NULL; in radeon_do_cleanup_cp()
1605 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); in radeon_do_cleanup_cp()
1619 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_resume_cp() local
1621 if (!dev_priv) { in radeon_do_resume_cp()
1629 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_resume_cp()
1631 radeon_set_pcigart(dev_priv, 0); in radeon_do_resume_cp()
1636 radeon_set_pcigart(dev_priv, 1); in radeon_do_resume_cp()
1639 radeon_cp_load_microcode(dev_priv); in radeon_do_resume_cp()
1640 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); in radeon_do_resume_cp()
1642 dev_priv->have_z_offset = 0; in radeon_do_resume_cp()
1653 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_init() local
1669 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_init()
1680 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_start() local
1685 if (dev_priv->cp_running) { in radeon_cp_start()
1689 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { in radeon_cp_start()
1691 dev_priv->cp_mode); in radeon_cp_start()
1695 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_start()
1696 r600_do_cp_start(dev_priv); in radeon_cp_start()
1698 radeon_do_cp_start(dev_priv); in radeon_cp_start()
1708 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_stop() local
1715 if (!dev_priv->cp_running) in radeon_cp_stop()
1722 radeon_do_cp_flush(dev_priv); in radeon_cp_stop()
1729 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1730 ret = r600_do_cp_idle(dev_priv); in radeon_cp_stop()
1732 ret = radeon_do_cp_idle(dev_priv); in radeon_cp_stop()
1741 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1742 r600_do_cp_stop(dev_priv); in radeon_cp_stop()
1744 radeon_do_cp_stop(dev_priv); in radeon_cp_stop()
1747 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1757 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_release() local
1760 if (dev_priv) { in radeon_do_release()
1761 if (dev_priv->cp_running) { in radeon_do_release()
1763 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_do_release()
1764 while ((ret = r600_do_cp_idle(dev_priv)) != 0) { in radeon_do_release()
1773 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { in radeon_do_release()
1782 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_do_release()
1783 r600_do_cp_stop(dev_priv); in radeon_do_release()
1786 radeon_do_cp_stop(dev_priv); in radeon_do_release()
1791 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { in radeon_do_release()
1793 if (dev_priv->mmio) /* remove this after permanent addmaps */ in radeon_do_release()
1796 if (dev_priv->mmio) { /* remove all surfaces */ in radeon_do_release()
1808 radeon_mem_takedown(&(dev_priv->gart_heap)); in radeon_do_release()
1809 radeon_mem_takedown(&(dev_priv->fb_heap)); in radeon_do_release()
1812 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_do_release()
1816 release_firmware(dev_priv->me_fw); in radeon_do_release()
1817 dev_priv->me_fw = NULL; in radeon_do_release()
1818 release_firmware(dev_priv->pfp_fw); in radeon_do_release()
1819 dev_priv->pfp_fw = NULL; in radeon_do_release()
1827 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_reset() local
1832 if (!dev_priv) { in radeon_cp_reset()
1837 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_reset()
1838 r600_do_cp_reset(dev_priv); in radeon_cp_reset()
1840 radeon_do_cp_reset(dev_priv); in radeon_cp_reset()
1843 dev_priv->cp_running = 0; in radeon_cp_reset()
1850 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_idle() local
1855 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_idle()
1856 return r600_do_cp_idle(dev_priv); in radeon_cp_idle()
1858 return radeon_do_cp_idle(dev_priv); in radeon_cp_idle()
1865 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_resume() local
1868 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_resume()
1876 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_engine_reset() local
1881 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_engine_reset()
1922 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_freelist_get() local
1928 if (++dev_priv->last_buf >= dma->buf_count) in radeon_freelist_get()
1929 dev_priv->last_buf = 0; in radeon_freelist_get()
1931 start = dev_priv->last_buf; in radeon_freelist_get()
1933 for (t = 0; t < dev_priv->usec_timeout; t++) { in radeon_freelist_get()
1934 u32 done_age = GET_SCRATCH(dev_priv, 1); in radeon_freelist_get()
1942 dev_priv->stats.requested_bufs++; in radeon_freelist_get()
1952 dev_priv->stats.freelist_loops++; in radeon_freelist_get()
1962 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_freelist_reset() local
1965 dev_priv->last_buf = 0; in radeon_freelist_reset()
1977 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) in radeon_wait_ring() argument
1979 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; in radeon_wait_ring()
1981 u32 last_head = GET_RING_HEAD(dev_priv); in radeon_wait_ring()
1983 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_wait_ring()
1984 u32 head = GET_RING_HEAD(dev_priv); in radeon_wait_ring()
1992 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_wait_ring()
2003 radeon_status(dev_priv); in radeon_wait_ring()
2070 drm_radeon_private_t *dev_priv; in radeon_driver_load() local
2073 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL); in radeon_driver_load()
2074 if (dev_priv == NULL) in radeon_driver_load()
2077 dev->dev_private = (void *)dev_priv; in radeon_driver_load()
2078 dev_priv->flags = flags; in radeon_driver_load()
2093 dev_priv->flags |= RADEON_HAS_HIERZ; in radeon_driver_load()
2103 dev_priv->flags |= RADEON_IS_AGP; in radeon_driver_load()
2105 dev_priv->flags |= RADEON_IS_PCIE; in radeon_driver_load()
2107 dev_priv->flags |= RADEON_IS_PCI; in radeon_driver_load()
2111 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); in radeon_driver_load()
2122 …((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"… in radeon_driver_load()
2179 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_firstopen() local
2181 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; in radeon_driver_firstopen()
2183 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0); in radeon_driver_firstopen()
2184 ret = drm_legacy_addmap(dev, dev_priv->fb_aper_offset, in radeon_driver_firstopen()
2195 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_unload() local
2199 drm_legacy_rmmap(dev, dev_priv->mmio); in radeon_driver_unload()
2201 kfree(dev_priv); in radeon_driver_unload()
2207 void radeon_commit_ring(drm_radeon_private_t *dev_priv) in radeon_commit_ring() argument
2215 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1); in radeon_commit_ring()
2219 ring = dev_priv->ring.start; in radeon_commit_ring()
2222 ring[dev_priv->ring.tail + i] = CP_PACKET2(); in radeon_commit_ring()
2224 dev_priv->ring.tail += i; in radeon_commit_ring()
2226 dev_priv->ring.space -= num_p2 * sizeof(u32); in radeon_commit_ring()
2229 dev_priv->ring.tail &= dev_priv->ring.tail_mask; in radeon_commit_ring()
2232 GET_RING_HEAD( dev_priv ); in radeon_commit_ring()
2234 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_commit_ring()
2235 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); in radeon_commit_ring()
2239 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); in radeon_commit_ring()