124 	RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));  in R500_READ_MCIND()
126 	RADEON_WRITE(R520_MC_IND_INDEX, 0);  in R500_READ_MCIND()
133 	RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);  in RS480_READ_MCIND()
135 	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);  in RS480_READ_MCIND()
142 	RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));  in RS690_READ_MCIND()
144 	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);  in RS690_READ_MCIND()
151 	RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |  in RS600_READ_MCIND()
191 		RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);  in radeon_write_fb_location()
193 		RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);  in radeon_write_fb_location()
204 		RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);  in radeon_write_fb_location()
211 		RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */  in radeon_write_agp_location()
212 		RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);  in radeon_write_agp_location()
214 		RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */  in radeon_write_agp_location()
215 		RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);  in radeon_write_agp_location()
226 		RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);  in radeon_write_agp_location()
237 		RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);  in radeon_write_agp_base()
239 		RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);  in radeon_write_agp_base()
255 		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);  in radeon_write_agp_base()
256 		RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);  in radeon_write_agp_base()
258 		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);  in radeon_write_agp_base()
260 			RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);  in radeon_write_agp_base()
272 		RADEON_WRITE(RADEON_BUS_CNTL, tmp);  in radeon_enable_bm()
279 		RADEON_WRITE(RADEON_BUS_CNTL, tmp);  in radeon_enable_bm()
334 		RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);  in radeon_do_pixcache_flush()
456 		RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));  in radeon_init_pipes()
458 	RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);  in radeon_init_pipes()
460 	RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);  in radeon_init_pipes()
461 	RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |  in radeon_init_pipes()
557 		RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);  in radeon_cp_load_microcode()
559 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,  in radeon_cp_load_microcode()
561 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,  in radeon_cp_load_microcode()
578 	RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);  in radeon_do_cp_flush()
610 	RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);  in radeon_do_cp_start()
652 	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);  in radeon_do_cp_reset()
676 	RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);  in radeon_do_cp_stop()
707 	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |  in radeon_do_engine_reset()
716 	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &  in radeon_do_engine_reset()
728 		RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);  in radeon_do_engine_reset()
729 		RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);  in radeon_do_engine_reset()
783 	RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);  in radeon_cp_init_ring_buffer()
786 	RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);  in radeon_cp_init_ring_buffer()
790 	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);  in radeon_cp_init_ring_buffer()
796 		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,  in radeon_cp_init_ring_buffer()
802 		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,  in radeon_cp_init_ring_buffer()
810 	RADEON_WRITE(RADEON_CP_RB_CNTL,  in radeon_cp_init_ring_buffer()
816 	RADEON_WRITE(RADEON_CP_RB_CNTL,  in radeon_cp_init_ring_buffer()
830 	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)  in radeon_cp_init_ring_buffer()
833 	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);  in radeon_cp_init_ring_buffer()
838 	RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);  in radeon_cp_init_ring_buffer()
841 	RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);  in radeon_cp_init_ring_buffer()
844 	RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);  in radeon_cp_init_ring_buffer()
857 	RADEON_WRITE(RADEON_ISYNC_CNTL,  in radeon_cp_init_ring_buffer()
877 	RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);  in radeon_test_writeback()
902 		RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |  in radeon_test_writeback()
904 		RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);  in radeon_test_writeback()
1109 		RADEON_WRITE(RADEON_AIC_CNTL,  in radeon_set_pcigart()
1114 		RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);  in radeon_set_pcigart()
1118 		RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);  in radeon_set_pcigart()
1119 		RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start  in radeon_set_pcigart()
1125 		RADEON_WRITE(RADEON_AGP_COMMAND, 0);	/* clear AGP_COMMAND */  in radeon_set_pcigart()
1127 		RADEON_WRITE(RADEON_AIC_CNTL,  in radeon_set_pcigart()
1163 		RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);  in radeon_setup_pcigart_surface()
1164 		RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);  in radeon_setup_pcigart_surface()
1165 		RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);  in radeon_setup_pcigart_surface()
1510 		RADEON_WRITE(RADEON_SURFACE_CNTL, 0);  in radeon_do_init_cp()
1515 		RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);  in radeon_do_init_cp()
1794 				RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);  in radeon_do_release()
1798 					RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);  in radeon_do_release()
1799 					RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +  in radeon_do_release()
1801 					RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +  in radeon_do_release()
2235 		RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);  in radeon_commit_ring()
2239 		RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);  in radeon_commit_ring()