748 		p1pll->pll_out_min = RBIOS32(pll_info + 0x12);  in radeon_combios_get_clock_info()
749 		p1pll->pll_out_max = RBIOS32(pll_info + 0x16);  in radeon_combios_get_clock_info()
754 			p1pll->pll_in_min = RBIOS32(pll_info + 0x36);  in radeon_combios_get_clock_info()
755 			p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);  in radeon_combios_get_clock_info()
765 		spll->pll_out_min = RBIOS32(pll_info + 0x1e);  in radeon_combios_get_clock_info()
766 		spll->pll_out_max = RBIOS32(pll_info + 0x22);  in radeon_combios_get_clock_info()
769 			spll->pll_in_min = RBIOS32(pll_info + 0x48);  in radeon_combios_get_clock_info()
770 			spll->pll_in_max = RBIOS32(pll_info + 0x4c);  in radeon_combios_get_clock_info()
780 		mpll->pll_out_min = RBIOS32(pll_info + 0x2a);  in radeon_combios_get_clock_info()
781 		mpll->pll_out_max = RBIOS32(pll_info + 0x2e);  in radeon_combios_get_clock_info()
784 			mpll->pll_in_min = RBIOS32(pll_info + 0x5a);  in radeon_combios_get_clock_info()
785 			mpll->pll_in_max = RBIOS32(pll_info + 0x5e);  in radeon_combios_get_clock_info()
803 		if (RBIOS32(pll_info + 0x16))  in radeon_combios_get_clock_info()
804 			rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);  in radeon_combios_get_clock_info()
1215 		panel_setup = RBIOS32(lcd_info + 0x39);  in radeon_combios_get_lvds_info()
1351 				    RBIOS32(tmds_info + i * 10 + 0x08);  in radeon_legacy_get_tmds_info_from_combios()
1365 				    RBIOS32(tmds_info + stride + 0x08);  in radeon_legacy_get_tmds_info_from_combios()
2566 								      RBIOS32(lcd_ddc_info + 3),  in radeon_get_legacy_connector_info_from_bios()
2567 								      RBIOS32(lcd_ddc_info + 7));  in radeon_get_legacy_connector_info_from_bios()
2574 								      RBIOS32(lcd_ddc_info + 3),  in radeon_get_legacy_connector_info_from_bios()
2575 								      RBIOS32(lcd_ddc_info + 7));  in radeon_get_legacy_connector_info_from_bios()
2732 			rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);  in radeon_combios_get_power_modes()
2733 			rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);  in radeon_combios_get_power_modes()
2907 						val = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2913 						and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2915 						or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2962 					val = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2967 					and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2969 					or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2982 					and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2984 					or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
3024 				val = RBIOS32(offset);  in combios_parse_mmio_table()
3029 				val = RBIOS32(offset);  in combios_parse_mmio_table()
3034 				and_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3036 				or_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3044 				and_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3046 				or_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3103 				val = RBIOS32(offset);  in combios_parse_pll_table()
3275 			mem_cntl = RBIOS32(offset + 1);  in combios_write_ram_size()