Lines Matching refs:u32

128 extern const u32 r600_utc[R600_PM_NUMBER_OF_TC];
129 extern const u32 r600_dtc[R600_PM_NUMBER_OF_TC];
131 void r600_dpm_print_class_info(u32 class, u32 class2);
132 void r600_dpm_print_cap_info(u32 caps);
135 u32 r600_dpm_get_vblank_time(struct radeon_device *rdev);
136 u32 r600_dpm_get_vrefresh(struct radeon_device *rdev);
137 bool r600_is_uvd_state(u32 class, u32 class2);
138 void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
139 			    u32 *p, u32 *u);
140 int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
151 void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p);
153 		 u32 l_to_m, u32 m_to_h,
154 		 u32 h_to_m, u32 m_to_l);
155 void r600_set_tc(struct radeon_device *rdev, u32 index, u32 u_t, u32 d_t);
157 void r600_set_vrc(struct radeon_device *rdev, u32 vrv);
158 void r600_set_tpu(struct radeon_device *rdev, u32 u);
159 void r600_set_tpc(struct radeon_device *rdev, u32 c);
160 void r600_set_sstu(struct radeon_device *rdev, u32 u);
161 void r600_set_sst(struct radeon_device *rdev, u32 t);
162 void r600_set_git(struct radeon_device *rdev, u32 t);
163 void r600_set_fctu(struct radeon_device *rdev, u32 u);
164 void r600_set_fct(struct radeon_device *rdev, u32 t);
165 void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p);
166 void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s);
167 void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u);
168 void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p);
169 void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s);
170 void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time);
171 void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time);
173 				    u32 index, bool enable);
175 						   u32 index, bool enable);
177 						 u32 index, bool enable);
179 					      u32 index, u32 divider);
181 						   u32 index, u32 divider);
183 						  u32 index, u32 divider);
185 					   u32 index, u32 step_time);
186 void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u);
187 void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u);
188 void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt);
198 					enum r600_power_level index, u32 voltage_index);
200 					  enum r600_power_level index, u32 mem_clock_index);
202 					  enum r600_power_level index, u32 eng_clock_index);
227 					       u32 sys_mask,
234 u8 r600_encode_pci_lane_width(u32 lanes);