Lines Matching refs:ix
530 u32 ix = 3 - (3 & index); in r600_voltage_control_program_voltages() local
532 WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff); in r600_voltage_control_program_voltages()
534 mask = 7 << (3 * ix); in r600_voltage_control_program_voltages()
536 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask); in r600_voltage_control_program_voltages()
561 u32 ix = 3 - (3 & index); in r600_power_level_enable() local
564 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE, in r600_power_level_enable()
567 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0, in r600_power_level_enable()
574 u32 ix = 3 - (3 & index); in r600_power_level_set_voltage_index() local
576 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_voltage_index()
583 u32 ix = 3 - (3 & index); in r600_power_level_set_mem_clock_index() local
585 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_mem_clock_index()
592 u32 ix = 3 - (3 & index); in r600_power_level_set_eng_clock_index() local
594 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_eng_clock_index()
602 u32 ix = 3 - (3 & index); in r600_power_level_set_watermark_id() local
607 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK); in r600_power_level_set_watermark_id()
613 u32 ix = 3 - (3 & index); in r600_power_level_set_pcie_gen2() local
618 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT); in r600_power_level_set_pcie_gen2()