2480 	u64 src_offset, dst_offset;  in r600_dma_cs_parse()  local
2503 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2504 				dst_offset <<= 8;  in r600_dma_cs_parse()
2509 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2510 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_dma_cs_parse()
2516 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2518 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2542 					dst_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2543 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2553 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2554 					dst_offset <<= 8;  in r600_dma_cs_parse()
2562 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2563 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2573 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2574 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;  in r600_dma_cs_parse()
2588 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2590 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2604 			dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2605 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in r600_dma_cs_parse()
2606 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2608 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()