Lines Matching refs:RADEON_WRITE
236 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_flush_gart_range()
237 …RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_si… in r600_vm_flush_gart_range()
238 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); in r600_vm_flush_gart_range()
255 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
256 …RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
257 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); in r600_vm_init()
264 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); in r600_vm_init()
265 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); in r600_vm_init()
267 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); in r600_vm_init()
268 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); in r600_vm_init()
270 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); in r600_vm_init()
271 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); in r600_vm_init()
273 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); in r600_vm_init()
274 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); in r600_vm_init()
276 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); in r600_vm_init()
277 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); in r600_vm_init()
279 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); in r600_vm_init()
280 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); in r600_vm_init()
282 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); in r600_vm_init()
283 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); in r600_vm_init()
287 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); in r600_vm_init()
289 RADEON_WRITE(R600_VM_L2_CNTL2, 0); in r600_vm_init()
293 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); in r600_vm_init()
297 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); in r600_vm_init()
303 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); in r600_vm_init()
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r600_vm_init()
306 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
307 …RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
401 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_load_microcode()
409 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); in r600_cp_load_microcode()
412 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); in r600_cp_load_microcode()
415 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
417 RADEON_WRITE(R600_CP_ME_RAM_DATA, in r600_cp_load_microcode()
421 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
423 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, in r600_cp_load_microcode()
426 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
427 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
428 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); in r600_cp_load_microcode()
440 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
441 …RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
442 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); in r700_vm_init()
451 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); in r700_vm_init()
452 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); in r700_vm_init()
453 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); in r700_vm_init()
454 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); in r700_vm_init()
455 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); in r700_vm_init()
456 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); in r700_vm_init()
457 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); in r700_vm_init()
461 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); in r700_vm_init()
463 RADEON_WRITE(R600_VM_L2_CNTL2, 0); in r700_vm_init()
465 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); in r700_vm_init()
469 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); in r700_vm_init()
475 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); in r700_vm_init()
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r700_vm_init()
478 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
479 …RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
494 RADEON_WRITE(R600_CP_RB_CNTL, in r700_cp_load_microcode()
502 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); in r700_cp_load_microcode()
505 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); in r700_cp_load_microcode()
508 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); in r700_cp_load_microcode()
510 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in r700_cp_load_microcode()
511 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); in r700_cp_load_microcode()
514 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); in r700_cp_load_microcode()
516 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in r700_cp_load_microcode()
517 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); in r700_cp_load_microcode()
519 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); in r700_cp_load_microcode()
520 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); in r700_cp_load_microcode()
521 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); in r700_cp_load_microcode()
537 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); in r600_test_writeback()
562 RADEON_WRITE(R600_CP_RB_CNTL, in r600_test_writeback()
568 RADEON_WRITE(R600_SCRATCH_UMSK, 0); in r600_test_writeback()
581 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); in r600_do_engine_reset()
583 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); in r600_do_engine_reset()
586 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); in r600_do_engine_reset()
589 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); in r600_do_engine_reset()
591 RADEON_WRITE(R600_CP_RB_CNTL, in r600_do_engine_reset()
597 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); in r600_do_engine_reset()
598 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); in r600_do_engine_reset()
599 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); in r600_do_engine_reset()
600 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); in r600_do_engine_reset()
826 RADEON_WRITE((0x2c14 + j), 0x00000000); in r600_gfx_init()
827 RADEON_WRITE((0x2c18 + j), 0x00000000); in r600_gfx_init()
828 RADEON_WRITE((0x2c1c + j), 0x00000000); in r600_gfx_init()
829 RADEON_WRITE((0x2c20 + j), 0x00000000); in r600_gfx_init()
830 RADEON_WRITE((0x2c24 + j), 0x00000000); in r600_gfx_init()
834 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); in r600_gfx_init()
889 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); in r600_gfx_init()
890 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in r600_gfx_init()
891 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in r600_gfx_init()
904 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); in r600_gfx_init()
905 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); in r600_gfx_init()
906 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); in r600_gfx_init()
910 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); in r600_gfx_init()
911 …RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MAS… in r600_gfx_init()
914 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | in r600_gfx_init()
917 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | in r600_gfx_init()
920 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | in r600_gfx_init()
926 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); in r600_gfx_init()
932 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); in r600_gfx_init()
940 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); in r600_gfx_init()
942 RADEON_WRITE(R600_DB_DEBUG, 0); in r600_gfx_init()
944 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | in r600_gfx_init()
948 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); in r600_gfx_init()
949 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); in r600_gfx_init()
951 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); in r600_gfx_init()
952 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); in r600_gfx_init()
968 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); in r600_gfx_init()
1050 RADEON_WRITE(R600_SQ_CONFIG, sq_config); in r600_gfx_init()
1051 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in r600_gfx_init()
1052 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in r600_gfx_init()
1053 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in r600_gfx_init()
1054 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in r600_gfx_init()
1055 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in r600_gfx_init()
1061 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); in r600_gfx_init()
1063 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); in r600_gfx_init()
1065 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | in r600_gfx_init()
1069 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | in r600_gfx_init()
1077 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | in r600_gfx_init()
1085 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | in r600_gfx_init()
1120 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); in r600_gfx_init()
1121 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); in r600_gfx_init()
1122 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); in r600_gfx_init()
1123 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); in r600_gfx_init()
1126 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); in r600_gfx_init()
1127 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); in r600_gfx_init()
1128 RADEON_WRITE(R600_SX_MISC, 0); in r600_gfx_init()
1129 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); in r600_gfx_init()
1130 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); in r600_gfx_init()
1131 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); in r600_gfx_init()
1132 RADEON_WRITE(R600_SPI_INPUT_Z, 0); in r600_gfx_init()
1133 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); in r600_gfx_init()
1134 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); in r600_gfx_init()
1137 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); in r600_gfx_init()
1138 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); in r600_gfx_init()
1139 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); in r600_gfx_init()
1140 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); in r600_gfx_init()
1141 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); in r600_gfx_init()
1142 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); in r600_gfx_init()
1143 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); in r600_gfx_init()
1144 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); in r600_gfx_init()
1165 RADEON_WRITE(R600_TC_CNTL, tc_cntl); in r600_gfx_init()
1168 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in r600_gfx_init()
1172 RADEON_WRITE(R600_ARB_POP, arb_pop); in r600_gfx_init()
1174 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); in r600_gfx_init()
1175 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | in r600_gfx_init()
1177 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); in r600_gfx_init()
1476 RADEON_WRITE((0x2c14 + j), 0x00000000); in r700_gfx_init()
1477 RADEON_WRITE((0x2c18 + j), 0x00000000); in r700_gfx_init()
1478 RADEON_WRITE((0x2c1c + j), 0x00000000); in r700_gfx_init()
1479 RADEON_WRITE((0x2c20 + j), 0x00000000); in r700_gfx_init()
1480 RADEON_WRITE((0x2c24 + j), 0x00000000); in r700_gfx_init()
1484 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); in r700_gfx_init()
1546 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); in r700_gfx_init()
1547 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in r700_gfx_init()
1548 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in r700_gfx_init()
1561 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); in r700_gfx_init()
1562 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); in r700_gfx_init()
1563 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); in r700_gfx_init()
1565 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); in r700_gfx_init()
1566 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); in r700_gfx_init()
1567 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); in r700_gfx_init()
1568 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); in r700_gfx_init()
1569 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); in r700_gfx_init()
1573 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); in r700_gfx_init()
1574 …RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MAS… in r700_gfx_init()
1577 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | in r700_gfx_init()
1580 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); in r700_gfx_init()
1583 RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); in r700_gfx_init()
1587 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); in r700_gfx_init()
1592 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); in r700_gfx_init()
1595 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | in r700_gfx_init()
1613 RADEON_WRITE(R700_DB_DEBUG3, db_debug3); in r700_gfx_init()
1618 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); in r700_gfx_init()
1621 …RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_si… in r700_gfx_init()
1625 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | in r700_gfx_init()
1629 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); in r700_gfx_init()
1631 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); in r700_gfx_init()
1633 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); in r700_gfx_init()
1635 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); in r700_gfx_init()
1637 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); in r700_gfx_init()
1653 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); in r700_gfx_init()
1674 RADEON_WRITE(R600_SQ_CONFIG, sq_config); in r700_gfx_init()
1676 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1680 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | in r700_gfx_init()
1690 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in r700_gfx_init()
1692 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1695 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1703 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1704 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1705 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1706 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1707 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1708 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1709 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1710 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); in r700_gfx_init()
1712 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | in r700_gfx_init()
1716 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | in r700_gfx_init()
1719 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | in r700_gfx_init()
1741 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); in r700_gfx_init()
1742 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); in r700_gfx_init()
1743 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); in r700_gfx_init()
1746 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); in r700_gfx_init()
1747 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); in r700_gfx_init()
1748 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); in r700_gfx_init()
1749 RADEON_WRITE(R600_SX_MISC, 0); in r700_gfx_init()
1750 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); in r700_gfx_init()
1751 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); in r700_gfx_init()
1752 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); in r700_gfx_init()
1753 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); in r700_gfx_init()
1754 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); in r700_gfx_init()
1755 RADEON_WRITE(R600_SPI_INPUT_Z, 0); in r700_gfx_init()
1756 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); in r700_gfx_init()
1757 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); in r700_gfx_init()
1760 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); in r700_gfx_init()
1761 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); in r700_gfx_init()
1762 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); in r700_gfx_init()
1763 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); in r700_gfx_init()
1764 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); in r700_gfx_init()
1765 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); in r700_gfx_init()
1766 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); in r700_gfx_init()
1767 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); in r700_gfx_init()
1769 RADEON_WRITE(R700_TCP_CNTL, 0); in r700_gfx_init()
1772 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in r700_gfx_init()
1774 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); in r700_gfx_init()
1776 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | in r700_gfx_init()
1794 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); in r600_cp_init_ring_buffer()
1797 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); in r600_cp_init_ring_buffer()
1802 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1808 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1814 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0); in r600_cp_init_ring_buffer()
1817 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); in r600_cp_init_ring_buffer()
1820 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1827 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1835 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); in r600_cp_init_ring_buffer()
1836 RADEON_WRITE(R600_CP_RB_WPTR, 0); in r600_cp_init_ring_buffer()
1852 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc)); in r600_cp_init_ring_buffer()
1853 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); in r600_cp_init_ring_buffer()
1856 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1861 RADEON_WRITE(R600_CP_RB_CNTL, in r600_cp_init_ring_buffer()
1886 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); in r600_cp_init_ring_buffer()
1888 RADEON_WRITE(R600_CP_ME_CNTL, 0xff); in r600_cp_init_ring_buffer()
1890 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); in r600_cp_init_ring_buffer()
1908 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); in r600_cp_init_ring_buffer()
1911 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); in r600_cp_init_ring_buffer()
1917 RADEON_WRITE(R600_LAST_FRAME_REG, 0); in r600_cp_init_ring_buffer()
1920 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); in r600_cp_init_ring_buffer()
1923 RADEON_WRITE(R600_LAST_CLEAR_REG, 0); in r600_cp_init_ring_buffer()
2350 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); in r600_do_cp_start()
2362 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); in r600_do_cp_reset()
2375 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); in r600_do_cp_stop()