Lines Matching refs:ring
1862 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r600_gfx_is_lockup() argument
1869 radeon_ring_lockup_update(rdev, ring); in r600_gfx_is_lockup()
1872 return radeon_ring_test_lockup(rdev, ring); in r600_gfx_is_lockup()
2370 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2565 struct radeon_ring *ring) in r600_gfx_get_rptr() argument
2570 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2578 struct radeon_ring *ring) in r600_gfx_get_wptr() argument
2588 struct radeon_ring *ring) in r600_gfx_set_wptr() argument
2590 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2638 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start() local
2642 r = radeon_ring_lock(rdev, ring, 7); in r600_cp_start()
2647 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2648 radeon_ring_write(ring, 0x1); in r600_cp_start()
2650 radeon_ring_write(ring, 0x0); in r600_cp_start()
2651 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2653 radeon_ring_write(ring, 0x3); in r600_cp_start()
2654 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2656 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2657 radeon_ring_write(ring, 0); in r600_cp_start()
2658 radeon_ring_write(ring, 0); in r600_cp_start()
2659 radeon_ring_unlock_commit(rdev, ring, false); in r600_cp_start()
2668 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume() local
2680 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2694 ring->wptr = 0; in r600_cp_resume()
2695 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2713 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2717 ring->ready = true; in r600_cp_resume()
2718 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2720 ring->ready = false; in r600_cp_resume()
2730 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) in r600_ring_init() argument
2738 ring->ring_size = ring_size; in r600_ring_init()
2739 ring->align_mask = 16 - 1; in r600_ring_init()
2741 if (radeon_ring_supports_scratch_reg(rdev, ring)) { in r600_ring_init()
2742 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2745 ring->rptr_save_reg = 0; in r600_ring_init()
2752 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini() local
2754 radeon_ring_fini(rdev, ring); in r600_cp_fini()
2755 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2773 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ring_test() argument
2786 r = radeon_ring_lock(rdev, ring, 3); in r600_ring_test()
2788 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in r600_ring_test()
2792 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2793 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2794 radeon_ring_write(ring, 0xDEADBEEF); in r600_ring_test()
2795 radeon_ring_unlock_commit(rdev, ring, false); in r600_ring_test()
2803 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in r600_ring_test()
2806 ring->idx, scratch, tmp); in r600_ring_test()
2820 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit() local
2828 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2830 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2831 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2832 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2833 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2834 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2836 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2837 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()
2838 radeon_ring_write(ring, lower_32_bits(addr)); in r600_fence_ring_emit()
2839 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
2840 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2841 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2844 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2845 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2846 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2847 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2848 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2849 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2850 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()
2852 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2853 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2854 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); in r600_fence_ring_emit()
2856 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2857 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2858 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2860 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
2861 radeon_ring_write(ring, RB_INT_STAT); in r600_fence_ring_emit()
2877 struct radeon_ring *ring, in r600_semaphore_ring_emit() argument
2887 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2888 radeon_ring_write(ring, lower_32_bits(addr)); in r600_semaphore_ring_emit()
2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); in r600_semaphore_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
2895 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
2922 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma() local
2931 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); in r600_copy_cpdma()
2939 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
2941 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2942 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2943 radeon_ring_write(ring, WAIT_3D_IDLE_bit); in r600_copy_cpdma()
2952 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma()
2953 radeon_ring_write(ring, lower_32_bits(src_offset)); in r600_copy_cpdma()
2954 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
2955 radeon_ring_write(ring, lower_32_bits(dst_offset)); in r600_copy_cpdma()
2956 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in r600_copy_cpdma()
2957 radeon_ring_write(ring, cur_size_in_bytes); in r600_copy_cpdma()
2961 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2962 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2963 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); in r600_copy_cpdma()
2965 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
2967 radeon_ring_unlock_undo(rdev, ring); in r600_copy_cpdma()
2972 radeon_ring_unlock_commit(rdev, ring, false); in r600_copy_cpdma()
2993 struct radeon_ring *ring; in r600_startup() local
3035 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_startup()
3053 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3054 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3067 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_startup()
3068 if (ring->ring_size) { in r600_startup()
3069 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in r600_startup()
3217 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3218 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3223 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_init()
3224 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_init()
3281 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute() local
3284 if (ring->rptr_save_reg) { in r600_ring_ib_execute()
3285 next_rptr = ring->wptr + 3 + 4; in r600_ring_ib_execute()
3286 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_ib_execute()
3287 radeon_ring_write(ring, ((ring->rptr_save_reg - in r600_ring_ib_execute()
3289 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3291 next_rptr = ring->wptr + 5 + 4; in r600_ring_ib_execute()
3292 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute()
3293 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_ring_ib_execute()
3294 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
3295 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3296 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
3299 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in r600_ring_ib_execute()
3300 radeon_ring_write(ring, in r600_ring_ib_execute()
3305 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
3306 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()
3309 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ib_test() argument
3323 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3349 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in r600_ib_test()
3411 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3432 rdev->ih.ring = NULL; in r600_ih_ring_fini()
4035 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4036 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()