Lines Matching refs:rdev
100 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
103 int r600_mc_wait_for_idle(struct radeon_device *rdev);
104 static void r600_gpu_init(struct radeon_device *rdev);
105 void r600_fini(struct radeon_device *rdev);
106 void r600_irq_disable(struct radeon_device *rdev);
107 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
108 extern int evergreen_rlc_resume(struct radeon_device *rdev);
109 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
121 int r600_get_allowed_info_register(struct radeon_device *rdev, in r600_get_allowed_info_register() argument
145 u32 r600_get_xclk(struct radeon_device *rdev) in r600_get_xclk() argument
147 return rdev->clock.spll.reference_freq; in r600_get_xclk()
150 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in r600_set_uvd_clocks() argument
164 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
174 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
179 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in r600_set_uvd_clocks()
185 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) in r600_set_uvd_clocks()
190 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
198 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
226 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
229 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
246 struct radeon_device *rdev = dev->dev_private; in dce3_program_fmt() local
297 int rv6xx_get_temp(struct radeon_device *rdev) in rv6xx_get_temp() argument
309 void r600_pm_get_dynpm_state(struct radeon_device *rdev) in r600_pm_get_dynpm_state() argument
313 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
314 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
317 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { in r600_pm_get_dynpm_state()
320 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
323 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
325 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
326 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
327 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
330 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
331 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
332 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
334 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
335 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
336 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
338 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
339 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
340 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
343 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
348 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
349 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
350 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
352 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
353 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
356 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
358 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
359 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
360 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
362 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
366 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
367 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
368 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
370 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
371 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
372 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
374 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
375 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
376 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
379 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
384 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
385 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
387 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
390 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
391 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
392 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
403 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
404 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
406 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
407 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
409 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
410 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
411 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
416 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
417 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
419 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
421 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
423 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
424 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
427 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
428 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
429 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
430 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
432 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
433 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
435 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
436 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
439 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
440 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
441 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
443 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
447 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
448 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
449 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
450 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
451 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
453 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
454 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
456 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
457 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
458 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
462 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
463 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
464 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
474 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
475 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
476 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
477 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
478 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
482 void rs780_pm_init_profile(struct radeon_device *rdev) in rs780_pm_init_profile() argument
484 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
491 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
501 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
502 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
506 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
507 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
508 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
509 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
511 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
512 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
513 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
514 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
516 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
517 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
518 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
519 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
520 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
522 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
523 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
537 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
543 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
547 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
548 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
558 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
559 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
563 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
564 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
565 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
566 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
568 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
569 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
570 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
571 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
573 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
574 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
575 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
576 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
578 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
579 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
580 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
581 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
583 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
584 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
585 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
586 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
588 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
589 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
590 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
591 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
595 void r600_pm_init_profile(struct radeon_device *rdev) in r600_pm_init_profile() argument
599 if (rdev->family == CHIP_R600) { in r600_pm_init_profile()
602 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
603 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
604 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
605 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
607 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
608 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
609 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
610 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
612 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
613 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
614 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
615 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
617 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
618 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
619 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
620 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
622 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
623 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
624 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
625 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
627 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
628 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
629 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
630 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
632 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
633 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
634 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
635 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
637 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
639 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
640 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
641 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
642 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
644 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
645 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
646 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
647 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
649 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
650 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
651 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
652 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
654 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
655 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
656 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
657 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
659 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
660 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
661 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
662 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
664 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
665 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
666 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
667 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
669 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
670 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
671 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
672 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
675 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
676 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
677 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
678 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
680 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
681 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in r600_pm_init_profile()
683 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
684 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
685 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
686 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
687 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
689 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
690 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
691 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
692 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
694 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in r600_pm_init_profile()
695 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
696 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
697 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
698 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
700 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
701 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); in r600_pm_init_profile()
703 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
704 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
705 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
706 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
707 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
709 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
710 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
711 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
712 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
714 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); in r600_pm_init_profile()
715 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
716 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
717 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
718 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
723 void r600_pm_misc(struct radeon_device *rdev) in r600_pm_misc() argument
725 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
726 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
727 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
734 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
735 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in r600_pm_misc()
736 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
742 bool r600_gui_idle(struct radeon_device *rdev) in r600_gui_idle() argument
751 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in r600_hpd_sense() argument
755 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_sense()
806 void r600_hpd_set_polarity(struct radeon_device *rdev, in r600_hpd_set_polarity() argument
810 bool connected = r600_hpd_sense(rdev, hpd); in r600_hpd_set_polarity()
812 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_set_polarity()
898 void r600_hpd_init(struct radeon_device *rdev) in r600_hpd_init() argument
900 struct drm_device *dev = rdev->ddev; in r600_hpd_init()
915 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_init()
917 if (ASIC_IS_DCE32(rdev)) in r600_hpd_init()
959 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
961 radeon_irq_kms_enable_hpd(rdev, enable); in r600_hpd_init()
964 void r600_hpd_fini(struct radeon_device *rdev) in r600_hpd_fini() argument
966 struct drm_device *dev = rdev->ddev; in r600_hpd_fini()
972 if (ASIC_IS_DCE3(rdev)) { in r600_hpd_fini()
1013 radeon_irq_kms_disable_hpd(rdev, disable); in r600_hpd_fini()
1019 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) in r600_pcie_gart_tlb_flush() argument
1025 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_pcie_gart_tlb_flush()
1026 !(rdev->flags & RADEON_IS_AGP)) { in r600_pcie_gart_tlb_flush()
1027 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1040 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1041 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1043 for (i = 0; i < rdev->usec_timeout; i++) { in r600_pcie_gart_tlb_flush()
1058 int r600_pcie_gart_init(struct radeon_device *rdev) in r600_pcie_gart_init() argument
1062 if (rdev->gart.robj) { in r600_pcie_gart_init()
1067 r = radeon_gart_init(rdev); in r600_pcie_gart_init()
1070 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1071 return radeon_gart_table_vram_alloc(rdev); in r600_pcie_gart_init()
1074 static int r600_pcie_gart_enable(struct radeon_device *rdev) in r600_pcie_gart_enable() argument
1079 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1080 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
1083 r = radeon_gart_table_vram_pin(rdev); in r600_pcie_gart_enable()
1114 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1115 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1116 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1120 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
1124 r600_pcie_gart_tlb_flush(rdev); in r600_pcie_gart_enable()
1126 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1127 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1128 rdev->gart.ready = true; in r600_pcie_gart_enable()
1132 static void r600_pcie_gart_disable(struct radeon_device *rdev) in r600_pcie_gart_disable() argument
1164 radeon_gart_table_vram_unpin(rdev); in r600_pcie_gart_disable()
1167 static void r600_pcie_gart_fini(struct radeon_device *rdev) in r600_pcie_gart_fini() argument
1169 radeon_gart_fini(rdev); in r600_pcie_gart_fini()
1170 r600_pcie_gart_disable(rdev); in r600_pcie_gart_fini()
1171 radeon_gart_table_vram_free(rdev); in r600_pcie_gart_fini()
1174 static void r600_agp_enable(struct radeon_device *rdev) in r600_agp_enable() argument
1208 int r600_mc_wait_for_idle(struct radeon_device *rdev) in r600_mc_wait_for_idle() argument
1213 for (i = 0; i < rdev->usec_timeout; i++) { in r600_mc_wait_for_idle()
1223 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs780_mc_rreg() argument
1228 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1232 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1236 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs780_mc_wreg() argument
1240 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1245 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1248 static void r600_mc_program(struct radeon_device *rdev) in r600_mc_program() argument
1264 rv515_mc_stop(rdev, &save); in r600_mc_program()
1265 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1266 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1271 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1272 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1275 rdev->mc.vram_start >> 12); in r600_mc_program()
1277 rdev->mc.gtt_end >> 12); in r600_mc_program()
1281 rdev->mc.gtt_start >> 12); in r600_mc_program()
1283 rdev->mc.vram_end >> 12); in r600_mc_program()
1286 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1287 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1289 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1290 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1291 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1293 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1296 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1297 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1298 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1299 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1305 if (r600_mc_wait_for_idle(rdev)) { in r600_mc_program()
1306 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1308 rv515_mc_resume(rdev, &save); in r600_mc_program()
1311 rv515_vga_render_disable(rdev); in r600_mc_program()
1335 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r600_vram_gtt_location() argument
1341 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1345 if (rdev->flags & RADEON_IS_AGP) { in r600_vram_gtt_location()
1350 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1357 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1364 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r600_vram_gtt_location()
1369 if (rdev->flags & RADEON_IS_IGP) { in r600_vram_gtt_location()
1373 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1374 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1375 radeon_gtt_location(rdev, mc); in r600_vram_gtt_location()
1379 static int r600_mc_init(struct radeon_device *rdev) in r600_mc_init() argument
1387 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1412 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1414 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1415 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1417 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1418 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1419 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1420 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1422 if (rdev->flags & RADEON_IS_IGP) { in r600_mc_init()
1423 rs690_pm_info(rdev); in r600_mc_init()
1424 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1426 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { in r600_mc_init()
1428 rdev->fastfb_working = false; in r600_mc_init()
1433 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1439 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1441 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1442 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
1443 rdev->fastfb_working = true; in r600_mc_init()
1449 radeon_update_bandwidth_info(rdev); in r600_mc_init()
1453 int r600_vram_scratch_init(struct radeon_device *rdev) in r600_vram_scratch_init() argument
1457 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1458 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, in r600_vram_scratch_init()
1460 0, NULL, NULL, &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1466 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1469 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1470 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1472 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1475 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1476 (void **)&rdev->vram_scratch.ptr); in r600_vram_scratch_init()
1478 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1479 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1484 void r600_vram_scratch_fini(struct radeon_device *rdev) in r600_vram_scratch_fini() argument
1488 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1491 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1493 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1494 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1495 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1497 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1500 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) in r600_set_bios_scratch_engine_hung() argument
1512 static void r600_print_gpu_status_regs(struct radeon_device *rdev) in r600_print_gpu_status_regs() argument
1514 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1516 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", in r600_print_gpu_status_regs()
1518 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1520 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in r600_print_gpu_status_regs()
1522 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in r600_print_gpu_status_regs()
1524 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1526 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1528 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in r600_print_gpu_status_regs()
1532 static bool r600_is_display_hung(struct radeon_device *rdev) in r600_is_display_hung() argument
1538 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1546 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1561 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) in r600_gpu_check_soft_reset() argument
1568 if (rdev->family >= CHIP_RV770) { in r600_gpu_check_soft_reset()
1618 if (r600_is_display_hung(rdev)) in r600_gpu_check_soft_reset()
1630 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in r600_gpu_soft_reset() argument
1639 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1641 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1644 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1661 rv515_mc_stop(rdev, &save); in r600_gpu_soft_reset()
1662 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_soft_reset()
1663 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1667 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1703 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1721 if (!(rdev->flags & RADEON_IS_IGP)) { in r600_gpu_soft_reset()
1732 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1746 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1760 rv515_mc_resume(rdev, &save); in r600_gpu_soft_reset()
1763 r600_print_gpu_status_regs(rdev); in r600_gpu_soft_reset()
1766 static void r600_gpu_pci_config_reset(struct radeon_device *rdev) in r600_gpu_pci_config_reset() argument
1771 dev_info(rdev->dev, "GPU pci config reset\n"); in r600_gpu_pci_config_reset()
1776 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1792 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1793 rv770_set_clk_bypass_mode(rdev); in r600_gpu_pci_config_reset()
1795 pci_clear_master(rdev->pdev); in r600_gpu_pci_config_reset()
1797 rv515_mc_stop(rdev, &save); in r600_gpu_pci_config_reset()
1798 if (r600_mc_wait_for_idle(rdev)) { in r600_gpu_pci_config_reset()
1799 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_pci_config_reset()
1810 radeon_pci_config_reset(rdev); in r600_gpu_pci_config_reset()
1820 for (i = 0; i < rdev->usec_timeout; i++) { in r600_gpu_pci_config_reset()
1827 int r600_asic_reset(struct radeon_device *rdev) in r600_asic_reset() argument
1831 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1834 r600_set_bios_scratch_engine_hung(rdev, true); in r600_asic_reset()
1837 r600_gpu_soft_reset(rdev, reset_mask); in r600_asic_reset()
1839 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1843 r600_gpu_pci_config_reset(rdev); in r600_asic_reset()
1845 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_asic_reset()
1848 r600_set_bios_scratch_engine_hung(rdev, false); in r600_asic_reset()
1862 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r600_gfx_is_lockup() argument
1864 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_gfx_is_lockup()
1869 radeon_ring_lockup_update(rdev, ring); in r600_gfx_is_lockup()
1872 return radeon_ring_test_lockup(rdev, ring); in r600_gfx_is_lockup()
1875 u32 r6xx_remap_render_backend(struct radeon_device *rdev, in r6xx_remap_render_backend() argument
1899 if (rdev->family <= CHIP_RV740) { in r6xx_remap_render_backend()
1930 static void r600_gpu_init(struct radeon_device *rdev) in r600_gpu_init() argument
1945 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1946 switch (rdev->family) { in r600_gpu_init()
1948 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1949 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1950 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1951 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1952 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
1953 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1954 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1955 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1956 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1957 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1958 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1959 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1960 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1964 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
1965 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
1966 rdev->config.r600.max_simds = 3; in r600_gpu_init()
1967 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1968 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1969 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1970 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1971 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1972 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1973 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1974 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1975 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1976 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1982 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
1983 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
1984 rdev->config.r600.max_simds = 2; in r600_gpu_init()
1985 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1986 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1987 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1988 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1989 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
1990 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1991 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1992 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1993 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1994 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
1997 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1998 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
1999 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2000 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2001 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2002 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2003 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2004 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2005 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2006 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2007 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2008 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2009 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2029 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2045 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2046 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2061 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2063 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2067 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2071 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2075 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2078 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2080 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2097 if (rdev->family == CHIP_RV670) in r600_gpu_init()
2102 if ((rdev->family > CHIP_R600)) in r600_gpu_init()
2106 if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2107 ((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2108 ((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2109 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2110 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2111 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2126 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2127 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2128 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2129 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2134 } else if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2135 ((rdev->family) == CHIP_RV630)) { in r600_gpu_init()
2156 if ((rdev->family) == CHIP_R600) { in r600_gpu_init()
2170 } else if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2171 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2172 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2173 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2190 } else if (((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2191 ((rdev->family) == CHIP_RV635)) { in r600_gpu_init()
2205 } else if ((rdev->family) == CHIP_RV670) { in r600_gpu_init()
2228 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2229 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2230 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2231 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2254 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2255 switch (rdev->family) { in r600_gpu_init()
2298 switch (rdev->family) { in r600_gpu_init()
2336 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) in r600_pciep_rreg() argument
2341 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2345 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2349 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r600_pciep_wreg() argument
2353 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2358 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2364 void r600_cp_stop(struct radeon_device *rdev) in r600_cp_stop() argument
2366 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_stop()
2367 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2370 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2373 int r600_init_microcode(struct radeon_device *rdev) in r600_init_microcode() argument
2384 switch (rdev->family) { in r600_init_microcode()
2478 if (rdev->family >= CHIP_CEDAR) { in r600_init_microcode()
2482 } else if (rdev->family >= CHIP_RV770) { in r600_init_microcode()
2495 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in r600_init_microcode()
2498 if (rdev->pfp_fw->size != pfp_req_size) { in r600_init_microcode()
2501 rdev->pfp_fw->size, fw_name); in r600_init_microcode()
2507 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r600_init_microcode()
2510 if (rdev->me_fw->size != me_req_size) { in r600_init_microcode()
2513 rdev->me_fw->size, fw_name); in r600_init_microcode()
2518 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in r600_init_microcode()
2521 if (rdev->rlc_fw->size != rlc_req_size) { in r600_init_microcode()
2524 rdev->rlc_fw->size, fw_name); in r600_init_microcode()
2528 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { in r600_init_microcode()
2530 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in r600_init_microcode()
2535 release_firmware(rdev->smc_fw); in r600_init_microcode()
2536 rdev->smc_fw = NULL; in r600_init_microcode()
2538 } else if (rdev->smc_fw->size != smc_req_size) { in r600_init_microcode()
2541 rdev->smc_fw->size, fw_name); in r600_init_microcode()
2552 release_firmware(rdev->pfp_fw); in r600_init_microcode()
2553 rdev->pfp_fw = NULL; in r600_init_microcode()
2554 release_firmware(rdev->me_fw); in r600_init_microcode()
2555 rdev->me_fw = NULL; in r600_init_microcode()
2556 release_firmware(rdev->rlc_fw); in r600_init_microcode()
2557 rdev->rlc_fw = NULL; in r600_init_microcode()
2558 release_firmware(rdev->smc_fw); in r600_init_microcode()
2559 rdev->smc_fw = NULL; in r600_init_microcode()
2564 u32 r600_gfx_get_rptr(struct radeon_device *rdev, in r600_gfx_get_rptr() argument
2569 if (rdev->wb.enabled) in r600_gfx_get_rptr()
2570 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2577 u32 r600_gfx_get_wptr(struct radeon_device *rdev, in r600_gfx_get_wptr() argument
2587 void r600_gfx_set_wptr(struct radeon_device *rdev, in r600_gfx_set_wptr() argument
2594 static int r600_cp_load_microcode(struct radeon_device *rdev) in r600_cp_load_microcode() argument
2599 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2602 r600_cp_stop(rdev); in r600_cp_load_microcode()
2618 fw_data = (const __be32 *)rdev->me_fw->data; in r600_cp_load_microcode()
2624 fw_data = (const __be32 *)rdev->pfp_fw->data; in r600_cp_load_microcode()
2636 int r600_cp_start(struct radeon_device *rdev) in r600_cp_start() argument
2638 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2642 r = radeon_ring_lock(rdev, ring, 7); in r600_cp_start()
2649 if (rdev->family >= CHIP_RV770) { in r600_cp_start()
2651 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2654 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2659 radeon_ring_unlock_commit(rdev, ring, false); in r600_cp_start()
2666 int r600_cp_resume(struct radeon_device *rdev) in r600_cp_resume() argument
2668 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2699 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2700 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2701 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2703 if (rdev->wb.enabled) in r600_cp_resume()
2716 r600_cp_start(rdev); in r600_cp_resume()
2718 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2724 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_resume()
2725 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()
2730 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) in r600_ring_init() argument
2741 if (radeon_ring_supports_scratch_reg(rdev, ring)) { in r600_ring_init()
2742 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2750 void r600_cp_fini(struct radeon_device *rdev) in r600_cp_fini() argument
2752 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini()
2753 r600_cp_stop(rdev); in r600_cp_fini()
2754 radeon_ring_fini(rdev, ring); in r600_cp_fini()
2755 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2761 void r600_scratch_init(struct radeon_device *rdev) in r600_scratch_init() argument
2765 rdev->scratch.num_reg = 7; in r600_scratch_init()
2766 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2767 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2768 rdev->scratch.free[i] = true; in r600_scratch_init()
2769 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2773 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ring_test() argument
2780 r = radeon_scratch_get(rdev, &scratch); in r600_ring_test()
2786 r = radeon_ring_lock(rdev, ring, 3); in r600_ring_test()
2789 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2795 radeon_ring_unlock_commit(rdev, ring, false); in r600_ring_test()
2796 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ring_test()
2802 if (i < rdev->usec_timeout) { in r600_ring_test()
2809 radeon_scratch_free(rdev, scratch); in r600_ring_test()
2817 void r600_fence_ring_emit(struct radeon_device *rdev, in r600_fence_ring_emit() argument
2820 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit()
2824 if (rdev->family >= CHIP_RV770) in r600_fence_ring_emit()
2827 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2828 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2857 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2876 bool r600_semaphore_ring_emit(struct radeon_device *rdev, in r600_semaphore_ring_emit() argument
2884 if (rdev->family < CHIP_CAYMAN) in r600_semaphore_ring_emit()
2892 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { in r600_semaphore_ring_emit()
2914 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, in r600_copy_cpdma() argument
2921 int ring_index = rdev->asic->copy.blit_ring_index; in r600_copy_cpdma()
2922 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma()
2931 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); in r600_copy_cpdma()
2934 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
2938 radeon_sync_resv(rdev, &sync, resv, false); in r600_copy_cpdma()
2939 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
2965 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
2967 radeon_ring_unlock_undo(rdev, ring); in r600_copy_cpdma()
2968 radeon_sync_free(rdev, &sync, NULL); in r600_copy_cpdma()
2972 radeon_ring_unlock_commit(rdev, ring, false); in r600_copy_cpdma()
2973 radeon_sync_free(rdev, &sync, fence); in r600_copy_cpdma()
2978 int r600_set_surface_reg(struct radeon_device *rdev, int reg, in r600_set_surface_reg() argument
2986 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) in r600_clear_surface_reg() argument
2991 static int r600_startup(struct radeon_device *rdev) in r600_startup() argument
2997 r600_pcie_gen2_enable(rdev); in r600_startup()
3000 r = r600_vram_scratch_init(rdev); in r600_startup()
3004 r600_mc_program(rdev); in r600_startup()
3006 if (rdev->flags & RADEON_IS_AGP) { in r600_startup()
3007 r600_agp_enable(rdev); in r600_startup()
3009 r = r600_pcie_gart_enable(rdev); in r600_startup()
3013 r600_gpu_init(rdev); in r600_startup()
3016 r = radeon_wb_init(rdev); in r600_startup()
3020 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_startup()
3022 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
3026 if (rdev->has_uvd) { in r600_startup()
3027 r = uvd_v1_0_resume(rdev); in r600_startup()
3029 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in r600_startup()
3031 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in r600_startup()
3035 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_startup()
3039 if (!rdev->irq.installed) { in r600_startup()
3040 r = radeon_irq_kms_init(rdev); in r600_startup()
3045 r = r600_irq_init(rdev); in r600_startup()
3048 radeon_irq_kms_fini(rdev); in r600_startup()
3051 r600_irq_set(rdev); in r600_startup()
3053 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3054 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3059 r = r600_cp_load_microcode(rdev); in r600_startup()
3062 r = r600_cp_resume(rdev); in r600_startup()
3066 if (rdev->has_uvd) { in r600_startup()
3067 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_startup()
3069 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in r600_startup()
3072 r = uvd_v1_0_init(rdev); in r600_startup()
3078 r = radeon_ib_pool_init(rdev); in r600_startup()
3080 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_startup()
3084 r = radeon_audio_init(rdev); in r600_startup()
3093 void r600_vga_set_state(struct radeon_device *rdev, bool state) in r600_vga_set_state() argument
3107 int r600_resume(struct radeon_device *rdev) in r600_resume() argument
3116 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
3118 if (rdev->pm.pm_method == PM_METHOD_DPM) in r600_resume()
3119 radeon_pm_resume(rdev); in r600_resume()
3121 rdev->accel_working = true; in r600_resume()
3122 r = r600_startup(rdev); in r600_resume()
3125 rdev->accel_working = false; in r600_resume()
3132 int r600_suspend(struct radeon_device *rdev) in r600_suspend() argument
3134 radeon_pm_suspend(rdev); in r600_suspend()
3135 radeon_audio_fini(rdev); in r600_suspend()
3136 r600_cp_stop(rdev); in r600_suspend()
3137 if (rdev->has_uvd) { in r600_suspend()
3138 uvd_v1_0_fini(rdev); in r600_suspend()
3139 radeon_uvd_suspend(rdev); in r600_suspend()
3141 r600_irq_suspend(rdev); in r600_suspend()
3142 radeon_wb_disable(rdev); in r600_suspend()
3143 r600_pcie_gart_disable(rdev); in r600_suspend()
3154 int r600_init(struct radeon_device *rdev) in r600_init() argument
3158 if (r600_debugfs_mc_info_init(rdev)) { in r600_init()
3162 if (!radeon_get_bios(rdev)) { in r600_init()
3163 if (ASIC_IS_AVIVO(rdev)) in r600_init()
3167 if (!rdev->is_atom_bios) { in r600_init()
3168 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in r600_init()
3171 r = radeon_atombios_init(rdev); in r600_init()
3175 if (!radeon_card_posted(rdev)) { in r600_init()
3176 if (!rdev->bios) { in r600_init()
3177 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in r600_init()
3181 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
3184 r600_scratch_init(rdev); in r600_init()
3186 radeon_surface_init(rdev); in r600_init()
3188 radeon_get_clock_info(rdev->ddev); in r600_init()
3190 r = radeon_fence_driver_init(rdev); in r600_init()
3193 if (rdev->flags & RADEON_IS_AGP) { in r600_init()
3194 r = radeon_agp_init(rdev); in r600_init()
3196 radeon_agp_disable(rdev); in r600_init()
3198 r = r600_mc_init(rdev); in r600_init()
3202 r = radeon_bo_init(rdev); in r600_init()
3206 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_init()
3207 r = r600_init_microcode(rdev); in r600_init()
3215 radeon_pm_init(rdev); in r600_init()
3217 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3218 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3220 if (rdev->has_uvd) { in r600_init()
3221 r = radeon_uvd_init(rdev); in r600_init()
3223 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_init()
3224 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_init()
3228 rdev->ih.ring_obj = NULL; in r600_init()
3229 r600_ih_ring_init(rdev, 64 * 1024); in r600_init()
3231 r = r600_pcie_gart_init(rdev); in r600_init()
3235 rdev->accel_working = true; in r600_init()
3236 r = r600_startup(rdev); in r600_init()
3238 dev_err(rdev->dev, "disabling GPU acceleration\n"); in r600_init()
3239 r600_cp_fini(rdev); in r600_init()
3240 r600_irq_fini(rdev); in r600_init()
3241 radeon_wb_fini(rdev); in r600_init()
3242 radeon_ib_pool_fini(rdev); in r600_init()
3243 radeon_irq_kms_fini(rdev); in r600_init()
3244 r600_pcie_gart_fini(rdev); in r600_init()
3245 rdev->accel_working = false; in r600_init()
3251 void r600_fini(struct radeon_device *rdev) in r600_fini() argument
3253 radeon_pm_fini(rdev); in r600_fini()
3254 radeon_audio_fini(rdev); in r600_fini()
3255 r600_cp_fini(rdev); in r600_fini()
3256 r600_irq_fini(rdev); in r600_fini()
3257 if (rdev->has_uvd) { in r600_fini()
3258 uvd_v1_0_fini(rdev); in r600_fini()
3259 radeon_uvd_fini(rdev); in r600_fini()
3261 radeon_wb_fini(rdev); in r600_fini()
3262 radeon_ib_pool_fini(rdev); in r600_fini()
3263 radeon_irq_kms_fini(rdev); in r600_fini()
3264 r600_pcie_gart_fini(rdev); in r600_fini()
3265 r600_vram_scratch_fini(rdev); in r600_fini()
3266 radeon_agp_fini(rdev); in r600_fini()
3267 radeon_gem_fini(rdev); in r600_fini()
3268 radeon_fence_driver_fini(rdev); in r600_fini()
3269 radeon_bo_fini(rdev); in r600_fini()
3270 radeon_atombios_fini(rdev); in r600_fini()
3271 kfree(rdev->bios); in r600_fini()
3272 rdev->bios = NULL; in r600_fini()
3279 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in r600_ring_ib_execute() argument
3281 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute()
3290 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3309 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r600_ib_test() argument
3317 r = radeon_scratch_get(rdev, &scratch); in r600_ib_test()
3323 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3332 r = radeon_ib_schedule(rdev, &ib, NULL, false); in r600_ib_test()
3342 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ib_test()
3348 if (i < rdev->usec_timeout) { in r600_ib_test()
3356 radeon_ib_free(rdev, &ib); in r600_ib_test()
3358 radeon_scratch_free(rdev, scratch); in r600_ib_test()
3373 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) in r600_ih_ring_init() argument
3380 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3381 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3382 rdev->ih.rptr = 0; in r600_ih_ring_init()
3385 int r600_ih_ring_alloc(struct radeon_device *rdev) in r600_ih_ring_alloc() argument
3390 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3391 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3394 NULL, NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3399 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3402 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3404 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
3406 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3410 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3411 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3412 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3421 void r600_ih_ring_fini(struct radeon_device *rdev) in r600_ih_ring_fini() argument
3424 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3425 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
3427 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
3428 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
3429 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
3431 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
3432 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3433 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
3437 void r600_rlc_stop(struct radeon_device *rdev) in r600_rlc_stop() argument
3440 if ((rdev->family >= CHIP_RV770) && in r600_rlc_stop()
3441 (rdev->family <= CHIP_RV740)) { in r600_rlc_stop()
3453 static void r600_rlc_start(struct radeon_device *rdev) in r600_rlc_start() argument
3458 static int r600_rlc_resume(struct radeon_device *rdev) in r600_rlc_resume() argument
3463 if (!rdev->rlc_fw) in r600_rlc_resume()
3466 r600_rlc_stop(rdev); in r600_rlc_resume()
3478 fw_data = (const __be32 *)rdev->rlc_fw->data; in r600_rlc_resume()
3479 if (rdev->family >= CHIP_RV770) { in r600_rlc_resume()
3492 r600_rlc_start(rdev); in r600_rlc_resume()
3497 static void r600_enable_interrupts(struct radeon_device *rdev) in r600_enable_interrupts() argument
3506 rdev->ih.enabled = true; in r600_enable_interrupts()
3509 void r600_disable_interrupts(struct radeon_device *rdev) in r600_disable_interrupts() argument
3521 rdev->ih.enabled = false; in r600_disable_interrupts()
3522 rdev->ih.rptr = 0; in r600_disable_interrupts()
3525 static void r600_disable_interrupt_state(struct radeon_device *rdev) in r600_disable_interrupt_state() argument
3536 if (ASIC_IS_DCE3(rdev)) { in r600_disable_interrupt_state()
3547 if (ASIC_IS_DCE32(rdev)) { in r600_disable_interrupt_state()
3578 int r600_irq_init(struct radeon_device *rdev) in r600_irq_init() argument
3585 ret = r600_ih_ring_alloc(rdev); in r600_irq_init()
3590 r600_disable_interrupts(rdev); in r600_irq_init()
3593 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3594 ret = evergreen_rlc_resume(rdev); in r600_irq_init()
3596 ret = r600_rlc_resume(rdev); in r600_irq_init()
3598 r600_ih_ring_fini(rdev); in r600_irq_init()
3604 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3614 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3615 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
3621 if (rdev->wb.enabled) in r600_irq_init()
3625 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3626 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3637 if (rdev->msi_enabled) in r600_irq_init()
3642 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3643 evergreen_disable_interrupt_state(rdev); in r600_irq_init()
3645 r600_disable_interrupt_state(rdev); in r600_irq_init()
3648 pci_set_master(rdev->pdev); in r600_irq_init()
3651 r600_enable_interrupts(rdev); in r600_irq_init()
3656 void r600_irq_suspend(struct radeon_device *rdev) in r600_irq_suspend() argument
3658 r600_irq_disable(rdev); in r600_irq_suspend()
3659 r600_rlc_stop(rdev); in r600_irq_suspend()
3662 void r600_irq_fini(struct radeon_device *rdev) in r600_irq_fini() argument
3664 r600_irq_suspend(rdev); in r600_irq_fini()
3665 r600_ih_ring_fini(rdev); in r600_irq_fini()
3668 int r600_irq_set(struct radeon_device *rdev) in r600_irq_set() argument
3678 if (!rdev->irq.installed) { in r600_irq_set()
3683 if (!rdev->ih.enabled) { in r600_irq_set()
3684 r600_disable_interrupts(rdev); in r600_irq_set()
3686 r600_disable_interrupt_state(rdev); in r600_irq_set()
3690 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3695 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3714 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3717 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3721 if (rdev->irq.dpm_thermal) { in r600_irq_set()
3726 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r600_irq_set()
3732 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in r600_irq_set()
3737 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3738 atomic_read(&rdev->irq.pflip[0])) { in r600_irq_set()
3742 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3743 atomic_read(&rdev->irq.pflip[1])) { in r600_irq_set()
3747 if (rdev->irq.hpd[0]) { in r600_irq_set()
3751 if (rdev->irq.hpd[1]) { in r600_irq_set()
3755 if (rdev->irq.hpd[2]) { in r600_irq_set()
3759 if (rdev->irq.hpd[3]) { in r600_irq_set()
3763 if (rdev->irq.hpd[4]) { in r600_irq_set()
3767 if (rdev->irq.hpd[5]) { in r600_irq_set()
3771 if (rdev->irq.afmt[0]) { in r600_irq_set()
3775 if (rdev->irq.afmt[1]) { in r600_irq_set()
3786 if (ASIC_IS_DCE3(rdev)) { in r600_irq_set()
3791 if (ASIC_IS_DCE32(rdev)) { in r600_irq_set()
3807 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3809 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3819 static void r600_irq_ack(struct radeon_device *rdev) in r600_irq_ack() argument
3823 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3824 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3825 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3826 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3827 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3828 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3829 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3831 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3832 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3835 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3836 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3837 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3838 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3839 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3841 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3842 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3844 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3846 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3848 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3850 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3852 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3854 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3856 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3857 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3867 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3868 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3878 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3879 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3889 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3894 if (ASIC_IS_DCE32(rdev)) { in r600_irq_ack()
3895 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3900 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3905 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3910 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3916 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3921 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3922 if (ASIC_IS_DCE3(rdev)) { in r600_irq_ack()
3935 void r600_irq_disable(struct radeon_device *rdev) in r600_irq_disable() argument
3937 r600_disable_interrupts(rdev); in r600_irq_disable()
3940 r600_irq_ack(rdev); in r600_irq_disable()
3941 r600_disable_interrupt_state(rdev); in r600_irq_disable()
3944 static u32 r600_get_ih_wptr(struct radeon_device *rdev) in r600_get_ih_wptr() argument
3948 if (rdev->wb.enabled) in r600_get_ih_wptr()
3949 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
3959 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in r600_get_ih_wptr()
3960 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in r600_get_ih_wptr()
3961 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
3966 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
3999 int r600_irq_process(struct radeon_device *rdev) in r600_irq_process() argument
4009 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
4013 if (!rdev->msi_enabled) in r600_irq_process()
4016 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4020 if (atomic_xchg(&rdev->ih.lock, 1)) in r600_irq_process()
4023 rptr = rdev->ih.rptr; in r600_irq_process()
4030 r600_irq_ack(rdev); in r600_irq_process()
4035 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4036 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
4042 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4045 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
4046 drm_handle_vblank(rdev->ddev, 0); in r600_irq_process()
4047 rdev->pm.vblank_sync = true; in r600_irq_process()
4048 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4050 if (atomic_read(&rdev->irq.pflip[0])) in r600_irq_process()
4051 radeon_crtc_handle_vblank(rdev, 0); in r600_irq_process()
4052 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4057 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4060 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4072 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4075 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
4076 drm_handle_vblank(rdev->ddev, 1); in r600_irq_process()
4077 rdev->pm.vblank_sync = true; in r600_irq_process()
4078 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4080 if (atomic_read(&rdev->irq.pflip[1])) in r600_irq_process()
4081 radeon_crtc_handle_vblank(rdev, 1); in r600_irq_process()
4082 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4087 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4090 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4102 radeon_crtc_handle_flip(rdev, 0); in r600_irq_process()
4107 radeon_crtc_handle_flip(rdev, 1); in r600_irq_process()
4112 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4115 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4120 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4123 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4128 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4131 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4136 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4139 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4144 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4147 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4152 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4155 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4168 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4171 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4177 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4180 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4192 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in r600_irq_process()
4198 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4202 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
4206 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in r600_irq_process()
4210 rdev->pm.dpm.thermal.high_to_low = false; in r600_irq_process()
4215 rdev->pm.dpm.thermal.high_to_low = true; in r600_irq_process()
4228 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
4232 schedule_work(&rdev->hotplug_work); in r600_irq_process()
4234 schedule_work(&rdev->audio_work); in r600_irq_process()
4235 if (queue_thermal && rdev->pm.dpm_enabled) in r600_irq_process()
4236 schedule_work(&rdev->pm.dpm.thermal.work); in r600_irq_process()
4237 rdev->ih.rptr = rptr; in r600_irq_process()
4238 atomic_set(&rdev->ih.lock, 0); in r600_irq_process()
4241 wptr = r600_get_ih_wptr(rdev); in r600_irq_process()
4257 struct radeon_device *rdev = dev->dev_private; in r600_debugfs_mc_info() local
4259 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); in r600_debugfs_mc_info()
4260 DREG32_SYS(m, rdev, VM_L2_STATUS); in r600_debugfs_mc_info()
4269 int r600_debugfs_mc_info_init(struct radeon_device *rdev) in r600_debugfs_mc_info_init() argument
4272 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); in r600_debugfs_mc_info_init()
4287 void r600_mmio_hdp_flush(struct radeon_device *rdev) in r600_mmio_hdp_flush() argument
4294 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_mmio_hdp_flush()
4295 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_mmio_hdp_flush()
4296 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; in r600_mmio_hdp_flush()
4305 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) in r600_set_pcie_lanes() argument
4309 if (rdev->flags & RADEON_IS_IGP) in r600_set_pcie_lanes()
4312 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_set_pcie_lanes()
4316 if (ASIC_IS_X2(rdev)) in r600_set_pcie_lanes()
4319 radeon_gui_idle(rdev); in r600_set_pcie_lanes()
4358 int r600_get_pcie_lanes(struct radeon_device *rdev) in r600_get_pcie_lanes() argument
4362 if (rdev->flags & RADEON_IS_IGP) in r600_get_pcie_lanes()
4365 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_get_pcie_lanes()
4369 if (ASIC_IS_X2(rdev)) in r600_get_pcie_lanes()
4372 radeon_gui_idle(rdev); in r600_get_pcie_lanes()
4395 static void r600_pcie_gen2_enable(struct radeon_device *rdev) in r600_pcie_gen2_enable() argument
4403 if (rdev->flags & RADEON_IS_IGP) in r600_pcie_gen2_enable()
4406 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_pcie_gen2_enable()
4410 if (ASIC_IS_X2(rdev)) in r600_pcie_gen2_enable()
4414 if (rdev->family <= CHIP_R600) in r600_pcie_gen2_enable()
4417 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in r600_pcie_gen2_enable()
4418 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in r600_pcie_gen2_enable()
4430 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4431 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4432 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4455 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4456 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4457 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4482 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4483 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4484 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4517 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) in r600_get_gpu_clock_counter() argument
4521 mutex_lock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()
4525 mutex_unlock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()