Lines Matching refs:radeon_ring_write
2647 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2648 radeon_ring_write(ring, 0x1); in r600_cp_start()
2650 radeon_ring_write(ring, 0x0); in r600_cp_start()
2651 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2653 radeon_ring_write(ring, 0x3); in r600_cp_start()
2654 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2656 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in r600_cp_start()
2657 radeon_ring_write(ring, 0); in r600_cp_start()
2658 radeon_ring_write(ring, 0); in r600_cp_start()
2792 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2793 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2794 radeon_ring_write(ring, 0xDEADBEEF); in r600_ring_test()
2830 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2831 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2832 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2833 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2834 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2836 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2837 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in r600_fence_ring_emit()
2838 radeon_ring_write(ring, lower_32_bits(addr)); in r600_fence_ring_emit()
2839 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
2840 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2841 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2844 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2845 radeon_ring_write(ring, cp_coher_cntl); in r600_fence_ring_emit()
2846 radeon_ring_write(ring, 0xFFFFFFFF); in r600_fence_ring_emit()
2847 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2848 radeon_ring_write(ring, 10); /* poll interval */ in r600_fence_ring_emit()
2849 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2850 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_fence_ring_emit()
2852 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2853 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2854 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); in r600_fence_ring_emit()
2856 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2857 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2858 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2860 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
2861 radeon_ring_write(ring, RB_INT_STAT); in r600_fence_ring_emit()
2887 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2888 radeon_ring_write(ring, lower_32_bits(addr)); in r600_semaphore_ring_emit()
2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); in r600_semaphore_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
2895 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
2941 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2942 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2943 radeon_ring_write(ring, WAIT_3D_IDLE_bit); in r600_copy_cpdma()
2952 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma()
2953 radeon_ring_write(ring, lower_32_bits(src_offset)); in r600_copy_cpdma()
2954 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
2955 radeon_ring_write(ring, lower_32_bits(dst_offset)); in r600_copy_cpdma()
2956 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in r600_copy_cpdma()
2957 radeon_ring_write(ring, cur_size_in_bytes); in r600_copy_cpdma()
2961 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
2962 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2963 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); in r600_copy_cpdma()
3286 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_ib_execute()
3287 radeon_ring_write(ring, ((ring->rptr_save_reg - in r600_ring_ib_execute()
3289 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3292 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute()
3293 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_ring_ib_execute()
3294 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
3295 radeon_ring_write(ring, next_rptr); in r600_ring_ib_execute()
3296 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
3299 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in r600_ring_ib_execute()
3300 radeon_ring_write(ring, in r600_ring_ib_execute()
3305 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
3306 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()