Lines Matching refs:r600
1945 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
1948 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1949 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
1950 rdev->config.r600.max_simds = 4; in r600_gpu_init()
1951 rdev->config.r600.max_backends = 4; in r600_gpu_init()
1952 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
1953 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1954 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
1955 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1956 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
1957 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1958 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1959 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1960 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1964 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
1965 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
1966 rdev->config.r600.max_simds = 3; in r600_gpu_init()
1967 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1968 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1969 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1970 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1971 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
1972 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1973 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1974 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1975 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1976 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
1982 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
1983 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
1984 rdev->config.r600.max_simds = 2; in r600_gpu_init()
1985 rdev->config.r600.max_backends = 1; in r600_gpu_init()
1986 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
1987 rdev->config.r600.max_threads = 192; in r600_gpu_init()
1988 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
1989 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
1990 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
1991 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
1992 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
1993 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
1994 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
1997 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
1998 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
1999 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2000 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2001 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2002 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2003 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2004 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2005 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2006 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2007 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2008 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2009 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2029 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2045 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2046 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2061 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2063 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2067 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2071 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2075 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2078 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2080 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2254 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2654 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
3824 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3825 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3826 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3828 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3829 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3831 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3832 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3835 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3836 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3837 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3838 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3839 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3841 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3842 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3844 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3846 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3848 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3850 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3852 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3854 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3856 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3867 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3878 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3889 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3895 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3900 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3905 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3910 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3916 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
3921 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4042 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4052 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4057 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4060 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4072 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4082 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4087 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4090 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4112 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4115 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4120 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4123 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4128 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4131 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4136 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4139 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4144 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4147 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4152 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4155 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4168 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4171 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4177 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4180 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()