4307 	u32 link_width_cntl, mask;  in r600_set_pcie_lanes()  local
4349 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_set_pcie_lanes()
4350 	link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;  in r600_set_pcie_lanes()
4351 	link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;  in r600_set_pcie_lanes()
4352 	link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |  in r600_set_pcie_lanes()
4355 	WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_set_pcie_lanes()
4360 	u32 link_width_cntl;  in r600_get_pcie_lanes()  local
4374 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_get_pcie_lanes()
4376 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF…  in r600_get_pcie_lanes()
4397 	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;  in r600_pcie_gen2_enable()  local
4434 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4435 		link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4436 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4437 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4438 		if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {  in r600_pcie_gen2_enable()
4439 			lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;  in r600_pcie_gen2_enable()
4440 			link_width_cntl &= ~(LC_LINK_WIDTH_MASK |  in r600_pcie_gen2_enable()
4442 			link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;  in r600_pcie_gen2_enable()
4443 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4445 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4446 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4499 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4502 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4504 			link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4505 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()