607 	struct radeon_bo_list *reloc;  in r300_packet0_check()  local
641 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
648 		track->cb[i].robj = reloc->robj;  in r300_packet0_check()
651 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
654 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
661 		track->zb.robj = reloc->robj;  in r300_packet0_check()
664 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
683 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
693 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
695 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
697 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
699 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
702 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
706 		track->textures[i].robj = reloc->robj;  in r300_packet0_check()
756 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
764 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
766 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
768 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
841 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
849 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
851 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
853 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
1056 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1063 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1098 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1105 		track->aa.robj = reloc->robj;  in r300_packet0_check()
1108 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1151 	struct radeon_bo_list *reloc;  in r300_packet3_check()  local
1167 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1173 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r300_packet3_check()
1174 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r300_packet3_check()