55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)  in rv370_pcie_gart_tlb_flush()  argument
89 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,  in rv370_pcie_gart_set_page()  argument
92 	void __iomem *ptr = rdev->gart.ptr;  in rv370_pcie_gart_set_page()
100 int rv370_pcie_gart_init(struct radeon_device *rdev)  in rv370_pcie_gart_init()  argument
104 	if (rdev->gart.robj) {  in rv370_pcie_gart_init()
109 	r = radeon_gart_init(rdev);  in rv370_pcie_gart_init()
112 	r = rv370_debugfs_pcie_gart_info_init(rdev);  in rv370_pcie_gart_init()
115 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;  in rv370_pcie_gart_init()
116 	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;  in rv370_pcie_gart_init()
117 	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;  in rv370_pcie_gart_init()
118 	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;  in rv370_pcie_gart_init()
119 	return radeon_gart_table_vram_alloc(rdev);  in rv370_pcie_gart_init()
122 int rv370_pcie_gart_enable(struct radeon_device *rdev)  in rv370_pcie_gart_enable()  argument
128 	if (rdev->gart.robj == NULL) {  in rv370_pcie_gart_enable()
129 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");  in rv370_pcie_gart_enable()
132 	r = radeon_gart_table_vram_pin(rdev);  in rv370_pcie_gart_enable()
138 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);  in rv370_pcie_gart_enable()
139 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;  in rv370_pcie_gart_enable()
143 	table_addr = rdev->gart.table_addr;  in rv370_pcie_gart_enable()
146 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);  in rv370_pcie_gart_enable()
154 	rv370_pcie_gart_tlb_flush(rdev);  in rv370_pcie_gart_enable()
156 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rv370_pcie_gart_enable()
158 	rdev->gart.ready = true;  in rv370_pcie_gart_enable()
162 void rv370_pcie_gart_disable(struct radeon_device *rdev)  in rv370_pcie_gart_disable()  argument
173 	radeon_gart_table_vram_unpin(rdev);  in rv370_pcie_gart_disable()
176 void rv370_pcie_gart_fini(struct radeon_device *rdev)  in rv370_pcie_gart_fini()  argument
178 	radeon_gart_fini(rdev);  in rv370_pcie_gart_fini()
179 	rv370_pcie_gart_disable(rdev);  in rv370_pcie_gart_fini()
180 	radeon_gart_table_vram_free(rdev);  in rv370_pcie_gart_fini()
183 void r300_fence_ring_emit(struct radeon_device *rdev,  in r300_fence_ring_emit()  argument
186 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in r300_fence_ring_emit()
206 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |  in r300_fence_ring_emit()
209 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);  in r300_fence_ring_emit()
211 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r300_fence_ring_emit()
217 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)  in r300_ring_start()  argument
224 	switch(rdev->num_gb_pipes) {  in r300_ring_start()
240 	r = radeon_ring_lock(rdev, ring, 64);  in r300_ring_start()
304 	radeon_ring_unlock_commit(rdev, ring, false);  in r300_ring_start()
307 static void r300_errata(struct radeon_device *rdev)  in r300_errata()  argument
309 	rdev->pll_errata = 0;  in r300_errata()
311 	if (rdev->family == CHIP_R300 &&  in r300_errata()
313 		rdev->pll_errata |= CHIP_ERRATA_R300_CG;  in r300_errata()
317 int r300_mc_wait_for_idle(struct radeon_device *rdev)  in r300_mc_wait_for_idle()  argument
322 	for (i = 0; i < rdev->usec_timeout; i++) {  in r300_mc_wait_for_idle()
333 static void r300_gpu_init(struct radeon_device *rdev)  in r300_gpu_init()  argument
337 	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||  in r300_gpu_init()
338 	    (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {  in r300_gpu_init()
340 		rdev->num_gb_pipes = 2;  in r300_gpu_init()
343 		rdev->num_gb_pipes = 1;  in r300_gpu_init()
345 	rdev->num_z_pipes = 1;  in r300_gpu_init()
347 	switch (rdev->num_gb_pipes) {  in r300_gpu_init()
364 	if (r100_gui_wait_for_idle(rdev)) {  in r300_gpu_init()
376 	if (r100_gui_wait_for_idle(rdev)) {  in r300_gpu_init()
380 	if (r300_mc_wait_for_idle(rdev)) {  in r300_gpu_init()
385 		 rdev->num_gb_pipes, rdev->num_z_pipes);  in r300_gpu_init()
388 int r300_asic_reset(struct radeon_device *rdev)  in r300_asic_reset()  argument
398 	r100_mc_stop(rdev, &save);  in r300_asic_reset()
400 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
409 	pci_save_state(rdev->pdev);  in r300_asic_reset()
411 	r100_bm_disable(rdev);  in r300_asic_reset()
419 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
431 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
433 	pci_restore_state(rdev->pdev);  in r300_asic_reset()
434 	r100_enable_bm(rdev);  in r300_asic_reset()
437 		dev_err(rdev->dev, "failed to reset GPU\n");  in r300_asic_reset()
440 		dev_info(rdev->dev, "GPU reset succeed\n");  in r300_asic_reset()
441 	r100_mc_resume(rdev, &save);  in r300_asic_reset()
448 void r300_mc_init(struct radeon_device *rdev)  in r300_mc_init()  argument
454 	rdev->mc.vram_is_ddr = true;  in r300_mc_init()
458 	case 0: rdev->mc.vram_width = 64; break;  in r300_mc_init()
459 	case 1: rdev->mc.vram_width = 128; break;  in r300_mc_init()
460 	case 2: rdev->mc.vram_width = 256; break;  in r300_mc_init()
461 	default:  rdev->mc.vram_width = 128; break;  in r300_mc_init()
463 	r100_vram_init_sizes(rdev);  in r300_mc_init()
464 	base = rdev->mc.aper_base;  in r300_mc_init()
465 	if (rdev->flags & RADEON_IS_IGP)  in r300_mc_init()
467 	radeon_vram_location(rdev, &rdev->mc, base);  in r300_mc_init()
468 	rdev->mc.gtt_base_align = 0;  in r300_mc_init()
469 	if (!(rdev->flags & RADEON_IS_AGP))  in r300_mc_init()
470 		radeon_gtt_location(rdev, &rdev->mc);  in r300_mc_init()
471 	radeon_update_bandwidth_info(rdev);  in r300_mc_init()
474 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)  in rv370_set_pcie_lanes()  argument
478 	if (rdev->flags & RADEON_IS_IGP)  in rv370_set_pcie_lanes()
481 	if (!(rdev->flags & RADEON_IS_PCIE))  in rv370_set_pcie_lanes()
533 int rv370_get_pcie_lanes(struct radeon_device *rdev)  in rv370_get_pcie_lanes()  argument
537 	if (rdev->flags & RADEON_IS_IGP)  in rv370_get_pcie_lanes()
540 	if (!(rdev->flags & RADEON_IS_PCIE))  in rv370_get_pcie_lanes()
569 	struct radeon_device *rdev = dev->dev_private;  in rv370_debugfs_pcie_gart_info()  local
594 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)  in rv370_debugfs_pcie_gart_info_init()  argument
597 	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);  in rv370_debugfs_pcie_gart_info_init()
724 		if (p->rdev->family < CHIP_RV515)  in r300_packet0_check()
731 		if (p->rdev->family < CHIP_RV515) {  in r300_packet0_check()
740 		    p->rdev->cmask_filp != p->filp) {  in r300_packet0_check()
790 			if (p->rdev->family < CHIP_RV515) {  in r300_packet0_check()
940 			if (p->rdev->family < CHIP_R420) {  in r300_packet0_check()
1007 		if (p->rdev->family >= CHIP_RV515) {  in r300_packet0_check()
1074 		if (p->rdev->hyperz_filp != p->filp) {  in r300_packet0_check()
1084 		if (p->rdev->hyperz_filp != p->filp) {  in r300_packet0_check()
1122 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1126 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1129 		if (p->rdev->family >= CHIP_RV350)  in r300_packet0_check()
1135 		if (p->rdev->family == CHIP_RV530)  in r300_packet0_check()
1190 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1205 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1212 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1219 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1226 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1233 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1240 		if (p->rdev->hyperz_filp != p->filp)  in r300_packet3_check()
1244 		if (p->rdev->cmask_filp != p->filp)  in r300_packet3_check()
1265 	r100_cs_track_clear(p->rdev, track);  in r300_cs_parse()
1276 						  p->rdev->config.r300.reg_safe_bm,  in r300_cs_parse()
1277 						  p->rdev->config.r300.reg_safe_bm_size,  in r300_cs_parse()
1296 void r300_set_reg_safe(struct radeon_device *rdev)  in r300_set_reg_safe()  argument
1298 	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;  in r300_set_reg_safe()
1299 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);  in r300_set_reg_safe()
1302 void r300_mc_program(struct radeon_device *rdev)  in r300_mc_program()  argument
1307 	r = r100_debugfs_mc_info_init(rdev);  in r300_mc_program()
1309 		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");  in r300_mc_program()
1313 	r100_mc_stop(rdev, &save);  in r300_mc_program()
1314 	if (rdev->flags & RADEON_IS_AGP) {  in r300_mc_program()
1316 			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |  in r300_mc_program()
1317 			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));  in r300_mc_program()
1318 		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));  in r300_mc_program()
1320 			upper_32_bits(rdev->mc.agp_base) & 0xff);  in r300_mc_program()
1327 	if (r300_mc_wait_for_idle(rdev))  in r300_mc_program()
1331 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |  in r300_mc_program()
1332 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));  in r300_mc_program()
1333 	r100_mc_resume(rdev, &save);  in r300_mc_program()
1336 void r300_clock_startup(struct radeon_device *rdev)  in r300_clock_startup()  argument
1341 		radeon_legacy_set_clock_gating(rdev, 1);  in r300_clock_startup()
1345 	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))  in r300_clock_startup()
1350 static int r300_startup(struct radeon_device *rdev)  in r300_startup()  argument
1355 	r100_set_common_regs(rdev);  in r300_startup()
1357 	r300_mc_program(rdev);  in r300_startup()
1359 	r300_clock_startup(rdev);  in r300_startup()
1361 	r300_gpu_init(rdev);  in r300_startup()
1364 	if (rdev->flags & RADEON_IS_PCIE) {  in r300_startup()
1365 		r = rv370_pcie_gart_enable(rdev);  in r300_startup()
1370 	if (rdev->family == CHIP_R300 ||  in r300_startup()
1371 	    rdev->family == CHIP_R350 ||  in r300_startup()
1372 	    rdev->family == CHIP_RV350)  in r300_startup()
1373 		r100_enable_bm(rdev);  in r300_startup()
1375 	if (rdev->flags & RADEON_IS_PCI) {  in r300_startup()
1376 		r = r100_pci_gart_enable(rdev);  in r300_startup()
1382 	r = radeon_wb_init(rdev);  in r300_startup()
1386 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);  in r300_startup()
1388 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in r300_startup()
1393 	if (!rdev->irq.installed) {  in r300_startup()
1394 		r = radeon_irq_kms_init(rdev);  in r300_startup()
1399 	r100_irq_set(rdev);  in r300_startup()
1400 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in r300_startup()
1402 	r = r100_cp_init(rdev, 1024 * 1024);  in r300_startup()
1404 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);  in r300_startup()
1408 	r = radeon_ib_pool_init(rdev);  in r300_startup()
1410 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in r300_startup()
1417 int r300_resume(struct radeon_device *rdev)  in r300_resume()  argument
1422 	if (rdev->flags & RADEON_IS_PCIE)  in r300_resume()
1423 		rv370_pcie_gart_disable(rdev);  in r300_resume()
1424 	if (rdev->flags & RADEON_IS_PCI)  in r300_resume()
1425 		r100_pci_gart_disable(rdev);  in r300_resume()
1427 	r300_clock_startup(rdev);  in r300_resume()
1429 	if (radeon_asic_reset(rdev)) {  in r300_resume()
1430 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r300_resume()
1435 	radeon_combios_asic_init(rdev->ddev);  in r300_resume()
1437 	r300_clock_startup(rdev);  in r300_resume()
1439 	radeon_surface_init(rdev);  in r300_resume()
1441 	rdev->accel_working = true;  in r300_resume()
1442 	r = r300_startup(rdev);  in r300_resume()
1444 		rdev->accel_working = false;  in r300_resume()
1449 int r300_suspend(struct radeon_device *rdev)  in r300_suspend()  argument
1451 	radeon_pm_suspend(rdev);  in r300_suspend()
1452 	r100_cp_disable(rdev);  in r300_suspend()
1453 	radeon_wb_disable(rdev);  in r300_suspend()
1454 	r100_irq_disable(rdev);  in r300_suspend()
1455 	if (rdev->flags & RADEON_IS_PCIE)  in r300_suspend()
1456 		rv370_pcie_gart_disable(rdev);  in r300_suspend()
1457 	if (rdev->flags & RADEON_IS_PCI)  in r300_suspend()
1458 		r100_pci_gart_disable(rdev);  in r300_suspend()
1462 void r300_fini(struct radeon_device *rdev)  in r300_fini()  argument
1464 	radeon_pm_fini(rdev);  in r300_fini()
1465 	r100_cp_fini(rdev);  in r300_fini()
1466 	radeon_wb_fini(rdev);  in r300_fini()
1467 	radeon_ib_pool_fini(rdev);  in r300_fini()
1468 	radeon_gem_fini(rdev);  in r300_fini()
1469 	if (rdev->flags & RADEON_IS_PCIE)  in r300_fini()
1470 		rv370_pcie_gart_fini(rdev);  in r300_fini()
1471 	if (rdev->flags & RADEON_IS_PCI)  in r300_fini()
1472 		r100_pci_gart_fini(rdev);  in r300_fini()
1473 	radeon_agp_fini(rdev);  in r300_fini()
1474 	radeon_irq_kms_fini(rdev);  in r300_fini()
1475 	radeon_fence_driver_fini(rdev);  in r300_fini()
1476 	radeon_bo_fini(rdev);  in r300_fini()
1477 	radeon_atombios_fini(rdev);  in r300_fini()
1478 	kfree(rdev->bios);  in r300_fini()
1479 	rdev->bios = NULL;  in r300_fini()
1482 int r300_init(struct radeon_device *rdev)  in r300_init()  argument
1487 	r100_vga_render_disable(rdev);  in r300_init()
1489 	radeon_scratch_init(rdev);  in r300_init()
1491 	radeon_surface_init(rdev);  in r300_init()
1494 	r100_restore_sanity(rdev);  in r300_init()
1496 	if (!radeon_get_bios(rdev)) {  in r300_init()
1497 		if (ASIC_IS_AVIVO(rdev))  in r300_init()
1500 	if (rdev->is_atom_bios) {  in r300_init()
1501 		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");  in r300_init()
1504 		r = radeon_combios_init(rdev);  in r300_init()
1509 	if (radeon_asic_reset(rdev)) {  in r300_init()
1510 		dev_warn(rdev->dev,  in r300_init()
1516 	if (radeon_boot_test_post_card(rdev) == false)  in r300_init()
1519 	r300_errata(rdev);  in r300_init()
1521 	radeon_get_clock_info(rdev->ddev);  in r300_init()
1523 	if (rdev->flags & RADEON_IS_AGP) {  in r300_init()
1524 		r = radeon_agp_init(rdev);  in r300_init()
1526 			radeon_agp_disable(rdev);  in r300_init()
1530 	r300_mc_init(rdev);  in r300_init()
1532 	r = radeon_fence_driver_init(rdev);  in r300_init()
1536 	r = radeon_bo_init(rdev);  in r300_init()
1539 	if (rdev->flags & RADEON_IS_PCIE) {  in r300_init()
1540 		r = rv370_pcie_gart_init(rdev);  in r300_init()
1544 	if (rdev->flags & RADEON_IS_PCI) {  in r300_init()
1545 		r = r100_pci_gart_init(rdev);  in r300_init()
1549 	r300_set_reg_safe(rdev);  in r300_init()
1552 	radeon_pm_init(rdev);  in r300_init()
1554 	rdev->accel_working = true;  in r300_init()
1555 	r = r300_startup(rdev);  in r300_init()
1558 		dev_err(rdev->dev, "Disabling GPU acceleration\n");  in r300_init()
1559 		r100_cp_fini(rdev);  in r300_init()
1560 		radeon_wb_fini(rdev);  in r300_init()
1561 		radeon_ib_pool_fini(rdev);  in r300_init()
1562 		radeon_irq_kms_fini(rdev);  in r300_init()
1563 		if (rdev->flags & RADEON_IS_PCIE)  in r300_init()
1564 			rv370_pcie_gart_fini(rdev);  in r300_init()
1565 		if (rdev->flags & RADEON_IS_PCI)  in r300_init()
1566 			r100_pci_gart_fini(rdev);  in r300_init()
1567 		radeon_agp_fini(rdev);  in r300_init()
1568 		rdev->accel_working = false;  in r300_init()