191 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));  in r300_fence_ring_emit()
192 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
193 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));  in r300_fence_ring_emit()
194 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
196 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
197 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH);  in r300_fence_ring_emit()
198 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
199 	radeon_ring_write(ring, R300_ZC_FLUSH);  in r300_fence_ring_emit()
201 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_fence_ring_emit()
202 	radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |  in r300_fence_ring_emit()
205 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
206 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |  in r300_fence_ring_emit()
208 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
209 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);  in r300_fence_ring_emit()
211 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r300_fence_ring_emit()
212 	radeon_ring_write(ring, fence->seq);  in r300_fence_ring_emit()
213 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r300_fence_ring_emit()
214 	radeon_ring_write(ring, RADEON_SW_INT_FIRE);  in r300_fence_ring_emit()
244 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r300_ring_start()
245 	radeon_ring_write(ring,  in r300_ring_start()
250 	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));  in r300_ring_start()
251 	radeon_ring_write(ring, gb_tile_config);  in r300_ring_start()
252 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
253 	radeon_ring_write(ring,  in r300_ring_start()
256 	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));  in r300_ring_start()
257 	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);  in r300_ring_start()
258 	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));  in r300_ring_start()
259 	radeon_ring_write(ring, 0);  in r300_ring_start()
260 	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));  in r300_ring_start()
261 	radeon_ring_write(ring, 0);  in r300_ring_start()
262 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
263 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);  in r300_ring_start()
264 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
265 	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);  in r300_ring_start()
266 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
267 	radeon_ring_write(ring,  in r300_ring_start()
270 	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));  in r300_ring_start()
271 	radeon_ring_write(ring, 0);  in r300_ring_start()
272 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
273 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);  in r300_ring_start()
274 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
275 	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);  in r300_ring_start()
276 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));  in r300_ring_start()
277 	radeon_ring_write(ring,  in r300_ring_start()
286 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));  in r300_ring_start()
287 	radeon_ring_write(ring,  in r300_ring_start()
295 	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));  in r300_ring_start()
296 	radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);  in r300_ring_start()
297 	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));  in r300_ring_start()
298 	radeon_ring_write(ring,  in r300_ring_start()
300 	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));  in r300_ring_start()
301 	radeon_ring_write(ring,  in r300_ring_start()