65 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);  in rv370_pcie_gart_tlb_flush()
67 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_tlb_flush()
137 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
138 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);  in rv370_pcie_gart_enable()
140 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);  in rv370_pcie_gart_enable()
141 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_enable()
142 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_enable()
144 	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);  in rv370_pcie_gart_enable()
146 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);  in rv370_pcie_gart_enable()
147 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);  in rv370_pcie_gart_enable()
149 	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);  in rv370_pcie_gart_enable()
153 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
166 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);  in rv370_pcie_gart_disable()
167 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);  in rv370_pcie_gart_disable()
168 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);  in rv370_pcie_gart_disable()
169 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);  in rv370_pcie_gart_disable()
172 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);  in rv370_pcie_gart_disable()
522 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in rv370_set_pcie_lanes()
523 	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |  in rv370_set_pcie_lanes()