Lines Matching refs:rdev
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) in r100_is_in_vblank() argument
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) in r100_is_counter_moving() argument
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) in r100_wait_for_vblank() argument
115 if (crtc >= rdev->num_crtc) in r100_wait_for_vblank()
129 while (r100_is_in_vblank(rdev, crtc)) { in r100_wait_for_vblank()
131 if (!r100_is_counter_moving(rdev, crtc)) in r100_wait_for_vblank()
136 while (!r100_is_in_vblank(rdev, crtc)) { in r100_wait_for_vblank()
138 if (!r100_is_counter_moving(rdev, crtc)) in r100_wait_for_vblank()
156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) in r100_page_flip() argument
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip()
167 for (i = 0; i < rdev->usec_timeout; i++) { in r100_page_flip()
189 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) in r100_page_flip_pending() argument
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending()
207 void r100_pm_get_dynpm_state(struct radeon_device *rdev) in r100_pm_get_dynpm_state() argument
210 rdev->pm.dynpm_can_upclock = true; in r100_pm_get_dynpm_state()
211 rdev->pm.dynpm_can_downclock = true; in r100_pm_get_dynpm_state()
213 switch (rdev->pm.dynpm_planned_action) { in r100_pm_get_dynpm_state()
215 rdev->pm.requested_power_state_index = 0; in r100_pm_get_dynpm_state()
216 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
219 if (rdev->pm.current_power_state_index == 0) { in r100_pm_get_dynpm_state()
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
221 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
223 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
224 for (i = 0; i < rdev->pm.num_power_states; i++) { in r100_pm_get_dynpm_state()
225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
227 else if (i >= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
231 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
236 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
237 rdev->pm.current_power_state_index - 1; in r100_pm_get_dynpm_state()
240 if ((rdev->pm.active_crtc_count > 0) && in r100_pm_get_dynpm_state()
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & in r100_pm_get_dynpm_state()
243 rdev->pm.requested_power_state_index++; in r100_pm_get_dynpm_state()
247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r100_pm_get_dynpm_state()
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
249 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
251 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r100_pm_get_dynpm_state()
253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
255 else if (i <= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
259 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
264 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
265 rdev->pm.current_power_state_index + 1; in r100_pm_get_dynpm_state()
269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r100_pm_get_dynpm_state()
270 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
278 rdev->pm.requested_clock_mode_index = 0; in r100_pm_get_dynpm_state()
281 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
282 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r100_pm_get_dynpm_state()
283 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
284 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r100_pm_get_dynpm_state()
285 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
298 void r100_pm_init_profile(struct radeon_device *rdev) in r100_pm_init_profile() argument
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
345 void r100_pm_misc(struct radeon_device *rdev) in r100_pm_misc() argument
347 int requested_index = rdev->pm.requested_power_state_index; in r100_pm_misc()
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in r100_pm_misc()
425 if ((rdev->flags & RADEON_IS_PCIE) && in r100_pm_misc()
426 !(rdev->flags & RADEON_IS_IGP) && in r100_pm_misc()
427 rdev->asic->pm.set_pcie_lanes && in r100_pm_misc()
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in r100_pm_misc()
430 radeon_set_pcie_lanes(rdev, in r100_pm_misc()
443 void r100_pm_prepare(struct radeon_device *rdev) in r100_pm_prepare() argument
445 struct drm_device *ddev = rdev->ddev; in r100_pm_prepare()
474 void r100_pm_finish(struct radeon_device *rdev) in r100_pm_finish() argument
476 struct drm_device *ddev = rdev->ddev; in r100_pm_finish()
506 bool r100_gui_idle(struct radeon_device *rdev) in r100_gui_idle() argument
524 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in r100_hpd_sense() argument
551 void r100_hpd_set_polarity(struct radeon_device *rdev, in r100_hpd_set_polarity() argument
555 bool connected = r100_hpd_sense(rdev, hpd); in r100_hpd_set_polarity()
587 void r100_hpd_init(struct radeon_device *rdev) in r100_hpd_init() argument
589 struct drm_device *dev = rdev->ddev; in r100_hpd_init()
596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r100_hpd_init()
598 radeon_irq_kms_enable_hpd(rdev, enable); in r100_hpd_init()
609 void r100_hpd_fini(struct radeon_device *rdev) in r100_hpd_fini() argument
611 struct drm_device *dev = rdev->ddev; in r100_hpd_fini()
619 radeon_irq_kms_disable_hpd(rdev, disable); in r100_hpd_fini()
625 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) in r100_pci_gart_tlb_flush() argument
633 int r100_pci_gart_init(struct radeon_device *rdev) in r100_pci_gart_init() argument
637 if (rdev->gart.ptr) { in r100_pci_gart_init()
642 r = radeon_gart_init(rdev); in r100_pci_gart_init()
645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
647 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
648 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
649 return radeon_gart_table_ram_alloc(rdev); in r100_pci_gart_init()
652 int r100_pci_gart_enable(struct radeon_device *rdev) in r100_pci_gart_enable() argument
660 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); in r100_pci_gart_enable()
661 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); in r100_pci_gart_enable()
663 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
666 r100_pci_gart_tlb_flush(rdev); in r100_pci_gart_enable()
668 (unsigned)(rdev->mc.gtt_size >> 20), in r100_pci_gart_enable()
669 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
670 rdev->gart.ready = true; in r100_pci_gart_enable()
674 void r100_pci_gart_disable(struct radeon_device *rdev) in r100_pci_gart_disable() argument
690 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, in r100_pci_gart_set_page() argument
693 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
697 void r100_pci_gart_fini(struct radeon_device *rdev) in r100_pci_gart_fini() argument
699 radeon_gart_fini(rdev); in r100_pci_gart_fini()
700 r100_pci_gart_disable(rdev); in r100_pci_gart_fini()
701 radeon_gart_table_ram_free(rdev); in r100_pci_gart_fini()
704 int r100_irq_set(struct radeon_device *rdev) in r100_irq_set() argument
708 if (!rdev->irq.installed) { in r100_irq_set()
713 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r100_irq_set()
716 if (rdev->irq.crtc_vblank_int[0] || in r100_irq_set()
717 atomic_read(&rdev->irq.pflip[0])) { in r100_irq_set()
720 if (rdev->irq.crtc_vblank_int[1] || in r100_irq_set()
721 atomic_read(&rdev->irq.pflip[1])) { in r100_irq_set()
724 if (rdev->irq.hpd[0]) { in r100_irq_set()
727 if (rdev->irq.hpd[1]) { in r100_irq_set()
738 void r100_irq_disable(struct radeon_device *rdev) in r100_irq_disable() argument
749 static uint32_t r100_irq_ack(struct radeon_device *rdev) in r100_irq_ack() argument
762 int r100_irq_process(struct radeon_device *rdev) in r100_irq_process() argument
767 status = r100_irq_ack(rdev); in r100_irq_process()
771 if (rdev->shutdown) { in r100_irq_process()
777 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r100_irq_process()
781 if (rdev->irq.crtc_vblank_int[0]) { in r100_irq_process()
782 drm_handle_vblank(rdev->ddev, 0); in r100_irq_process()
783 rdev->pm.vblank_sync = true; in r100_irq_process()
784 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
786 if (atomic_read(&rdev->irq.pflip[0])) in r100_irq_process()
787 radeon_crtc_handle_vblank(rdev, 0); in r100_irq_process()
790 if (rdev->irq.crtc_vblank_int[1]) { in r100_irq_process()
791 drm_handle_vblank(rdev->ddev, 1); in r100_irq_process()
792 rdev->pm.vblank_sync = true; in r100_irq_process()
793 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
795 if (atomic_read(&rdev->irq.pflip[1])) in r100_irq_process()
796 radeon_crtc_handle_vblank(rdev, 1); in r100_irq_process()
806 status = r100_irq_ack(rdev); in r100_irq_process()
809 schedule_work(&rdev->hotplug_work); in r100_irq_process()
810 if (rdev->msi_enabled) { in r100_irq_process()
811 switch (rdev->family) { in r100_irq_process()
826 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) in r100_get_vblank_counter() argument
839 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) in r100_ring_hdp_flush() argument
842 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_ring_hdp_flush()
845 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_ring_hdp_flush()
850 void r100_fence_ring_emit(struct radeon_device *rdev, in r100_fence_ring_emit() argument
853 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r100_fence_ring_emit()
864 r100_ring_hdp_flush(rdev, ring); in r100_fence_ring_emit()
866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
872 bool r100_semaphore_ring_emit(struct radeon_device *rdev, in r100_semaphore_ring_emit() argument
882 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, in r100_copy_blit() argument
888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_copy_blit()
907 r = radeon_ring_lock(rdev, ring, ndw); in r100_copy_blit()
950 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); in r100_copy_blit()
952 radeon_ring_unlock_undo(rdev, ring); in r100_copy_blit()
955 radeon_ring_unlock_commit(rdev, ring, false); in r100_copy_blit()
959 static int r100_cp_wait_for_idle(struct radeon_device *rdev) in r100_cp_wait_for_idle() argument
964 for (i = 0; i < rdev->usec_timeout; i++) { in r100_cp_wait_for_idle()
974 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) in r100_ring_start() argument
978 r = radeon_ring_lock(rdev, ring, 2); in r100_ring_start()
988 radeon_ring_unlock_commit(rdev, ring, false); in r100_ring_start()
993 static int r100_cp_init_microcode(struct radeon_device *rdev) in r100_cp_init_microcode() argument
1000 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || in r100_cp_init_microcode()
1001 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || in r100_cp_init_microcode()
1002 (rdev->family == CHIP_RS200)) { in r100_cp_init_microcode()
1005 } else if ((rdev->family == CHIP_R200) || in r100_cp_init_microcode()
1006 (rdev->family == CHIP_RV250) || in r100_cp_init_microcode()
1007 (rdev->family == CHIP_RV280) || in r100_cp_init_microcode()
1008 (rdev->family == CHIP_RS300)) { in r100_cp_init_microcode()
1011 } else if ((rdev->family == CHIP_R300) || in r100_cp_init_microcode()
1012 (rdev->family == CHIP_R350) || in r100_cp_init_microcode()
1013 (rdev->family == CHIP_RV350) || in r100_cp_init_microcode()
1014 (rdev->family == CHIP_RV380) || in r100_cp_init_microcode()
1015 (rdev->family == CHIP_RS400) || in r100_cp_init_microcode()
1016 (rdev->family == CHIP_RS480)) { in r100_cp_init_microcode()
1019 } else if ((rdev->family == CHIP_R420) || in r100_cp_init_microcode()
1020 (rdev->family == CHIP_R423) || in r100_cp_init_microcode()
1021 (rdev->family == CHIP_RV410)) { in r100_cp_init_microcode()
1024 } else if ((rdev->family == CHIP_RS690) || in r100_cp_init_microcode()
1025 (rdev->family == CHIP_RS740)) { in r100_cp_init_microcode()
1028 } else if (rdev->family == CHIP_RS600) { in r100_cp_init_microcode()
1031 } else if ((rdev->family == CHIP_RV515) || in r100_cp_init_microcode()
1032 (rdev->family == CHIP_R520) || in r100_cp_init_microcode()
1033 (rdev->family == CHIP_RV530) || in r100_cp_init_microcode()
1034 (rdev->family == CHIP_R580) || in r100_cp_init_microcode()
1035 (rdev->family == CHIP_RV560) || in r100_cp_init_microcode()
1036 (rdev->family == CHIP_RV570)) { in r100_cp_init_microcode()
1041 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r100_cp_init_microcode()
1045 } else if (rdev->me_fw->size % 8) { in r100_cp_init_microcode()
1048 rdev->me_fw->size, fw_name); in r100_cp_init_microcode()
1050 release_firmware(rdev->me_fw); in r100_cp_init_microcode()
1051 rdev->me_fw = NULL; in r100_cp_init_microcode()
1056 u32 r100_gfx_get_rptr(struct radeon_device *rdev, in r100_gfx_get_rptr() argument
1061 if (rdev->wb.enabled) in r100_gfx_get_rptr()
1062 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); in r100_gfx_get_rptr()
1069 u32 r100_gfx_get_wptr(struct radeon_device *rdev, in r100_gfx_get_wptr() argument
1079 void r100_gfx_set_wptr(struct radeon_device *rdev, in r100_gfx_set_wptr() argument
1086 static void r100_cp_load_microcode(struct radeon_device *rdev) in r100_cp_load_microcode() argument
1091 if (r100_gui_wait_for_idle(rdev)) { in r100_cp_load_microcode()
1096 if (rdev->me_fw) { in r100_cp_load_microcode()
1097 size = rdev->me_fw->size / 4; in r100_cp_load_microcode()
1098 fw_data = (const __be32 *)&rdev->me_fw->data[0]; in r100_cp_load_microcode()
1109 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) in r100_cp_init() argument
1111 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_cp_init()
1122 if (r100_debugfs_cp_init(rdev)) { in r100_cp_init()
1125 if (!rdev->me_fw) { in r100_cp_init()
1126 r = r100_cp_init_microcode(rdev); in r100_cp_init()
1136 r100_cp_load_microcode(rdev); in r100_cp_init()
1137 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, in r100_cp_init()
1187 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1188 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
1190 if (rdev->wb.enabled) in r100_cp_init()
1208 pci_set_master(rdev->pdev); in r100_cp_init()
1210 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_init()
1211 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r100_cp_init()
1217 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r100_cp_init()
1220 && radeon_ring_supports_scratch_reg(rdev, ring)) { in r100_cp_init()
1221 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r100_cp_init()
1230 void r100_cp_fini(struct radeon_device *rdev) in r100_cp_fini() argument
1232 if (r100_cp_wait_for_idle(rdev)) { in r100_cp_fini()
1236 r100_cp_disable(rdev); in r100_cp_fini()
1237 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); in r100_cp_fini()
1238 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_fini()
1242 void r100_cp_disable(struct radeon_device *rdev) in r100_cp_disable() argument
1245 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r100_cp_disable()
1246 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_cp_disable()
1250 if (r100_gui_wait_for_idle(rdev)) { in r100_cp_disable()
1465 crtc = drm_crtc_find(p->rdev->ddev, crtc_id); in r100_cs_packet_parse_vline()
1961 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1973 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1985 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1992 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1999 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2006 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2013 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2020 if (p->rdev->hyperz_filp != p->filp) in r100_packet3_check()
2041 r100_cs_track_clear(p->rdev, track); in r100_cs_parse()
2051 if (p->rdev->family >= CHIP_R200) in r100_cs_parse()
2053 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2054 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2058 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2059 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2125 static int r100_cs_track_cube(struct radeon_device *rdev, in r100_cs_track_cube() argument
2156 static int r100_cs_track_texture_check(struct radeon_device *rdev, in r100_cs_track_texture_check() argument
2177 if (rdev->family < CHIP_R300) in r100_cs_track_texture_check()
2183 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2190 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2217 ret = r100_cs_track_cube(rdev, track, u); in r100_cs_track_texture_check()
2238 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) in r100_cs_track_check() argument
2324 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2343 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2370 return r100_cs_track_texture_check(rdev, track); in r100_cs_track_check()
2375 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) in r100_cs_track_clear() argument
2384 if (rdev->family < CHIP_R300) { in r100_cs_track_clear()
2386 if (rdev->family <= CHIP_RS200) in r100_cs_track_clear()
2428 if (rdev->family <= CHIP_RS200) { in r100_cs_track_clear()
2455 static void r100_errata(struct radeon_device *rdev) in r100_errata() argument
2457 rdev->pll_errata = 0; in r100_errata()
2459 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { in r100_errata()
2460 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; in r100_errata()
2463 if (rdev->family == CHIP_RV100 || in r100_errata()
2464 rdev->family == CHIP_RS100 || in r100_errata()
2465 rdev->family == CHIP_RS200) { in r100_errata()
2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; in r100_errata()
2470 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) in r100_rbbm_fifo_wait_for_entry() argument
2475 for (i = 0; i < rdev->usec_timeout; i++) { in r100_rbbm_fifo_wait_for_entry()
2485 int r100_gui_wait_for_idle(struct radeon_device *rdev) in r100_gui_wait_for_idle() argument
2490 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { in r100_gui_wait_for_idle()
2494 for (i = 0; i < rdev->usec_timeout; i++) { in r100_gui_wait_for_idle()
2504 int r100_mc_wait_for_idle(struct radeon_device *rdev) in r100_mc_wait_for_idle() argument
2509 for (i = 0; i < rdev->usec_timeout; i++) { in r100_mc_wait_for_idle()
2520 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in r100_gpu_is_lockup() argument
2526 radeon_ring_lockup_update(rdev, ring); in r100_gpu_is_lockup()
2529 return radeon_ring_test_lockup(rdev, ring); in r100_gpu_is_lockup()
2533 void r100_enable_bm(struct radeon_device *rdev) in r100_enable_bm() argument
2541 void r100_bm_disable(struct radeon_device *rdev) in r100_bm_disable() argument
2554 pci_clear_master(rdev->pdev); in r100_bm_disable()
2558 int r100_asic_reset(struct radeon_device *rdev) in r100_asic_reset() argument
2568 r100_mc_stop(rdev, &save); in r100_asic_reset()
2570 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2579 pci_save_state(rdev->pdev); in r100_asic_reset()
2581 r100_bm_disable(rdev); in r100_asic_reset()
2591 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2599 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2601 pci_restore_state(rdev->pdev); in r100_asic_reset()
2602 r100_enable_bm(rdev); in r100_asic_reset()
2606 dev_err(rdev->dev, "failed to reset GPU\n"); in r100_asic_reset()
2609 dev_info(rdev->dev, "GPU reset succeed\n"); in r100_asic_reset()
2610 r100_mc_resume(rdev, &save); in r100_asic_reset()
2614 void r100_set_common_regs(struct radeon_device *rdev) in r100_set_common_regs() argument
2616 struct drm_device *dev = rdev->ddev; in r100_set_common_regs()
2701 static void r100_vram_get_type(struct radeon_device *rdev) in r100_vram_get_type() argument
2705 rdev->mc.vram_is_ddr = false; in r100_vram_get_type()
2706 if (rdev->flags & RADEON_IS_IGP) in r100_vram_get_type()
2707 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2709 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2710 if ((rdev->family == CHIP_RV100) || in r100_vram_get_type()
2711 (rdev->family == CHIP_RS100) || in r100_vram_get_type()
2712 (rdev->family == CHIP_RS200)) { in r100_vram_get_type()
2715 rdev->mc.vram_width = 32; in r100_vram_get_type()
2717 rdev->mc.vram_width = 64; in r100_vram_get_type()
2719 if (rdev->flags & RADEON_SINGLE_CRTC) { in r100_vram_get_type()
2720 rdev->mc.vram_width /= 4; in r100_vram_get_type()
2721 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2723 } else if (rdev->family <= CHIP_RV280) { in r100_vram_get_type()
2726 rdev->mc.vram_width = 128; in r100_vram_get_type()
2728 rdev->mc.vram_width = 64; in r100_vram_get_type()
2732 rdev->mc.vram_width = 128; in r100_vram_get_type()
2736 static u32 r100_get_accessible_vram(struct radeon_device *rdev) in r100_get_accessible_vram() argument
2746 if (rdev->family == CHIP_RV280 || in r100_get_accessible_vram()
2747 rdev->family >= CHIP_RV350) { in r100_get_accessible_vram()
2758 pci_read_config_byte(rdev->pdev, 0xe, &byte); in r100_get_accessible_vram()
2774 void r100_vram_init_sizes(struct radeon_device *rdev) in r100_vram_init_sizes() argument
2779 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r100_vram_init_sizes()
2780 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r100_vram_init_sizes()
2781 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); in r100_vram_init_sizes()
2783 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) in r100_vram_init_sizes()
2784 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2786 if (rdev->flags & RADEON_IS_IGP) { in r100_vram_init_sizes()
2790 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); in r100_vram_init_sizes()
2791 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2792 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2794 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2798 if (rdev->mc.real_vram_size == 0) { in r100_vram_init_sizes()
2799 rdev->mc.real_vram_size = 8192 * 1024; in r100_vram_init_sizes()
2800 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2805 if (rdev->mc.aper_size > config_aper_size) in r100_vram_init_sizes()
2806 config_aper_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2808 if (config_aper_size > rdev->mc.real_vram_size) in r100_vram_init_sizes()
2809 rdev->mc.mc_vram_size = config_aper_size; in r100_vram_init_sizes()
2811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2815 void r100_vga_set_state(struct radeon_device *rdev, bool state) in r100_vga_set_state() argument
2829 static void r100_mc_init(struct radeon_device *rdev) in r100_mc_init() argument
2833 r100_vram_get_type(rdev); in r100_mc_init()
2834 r100_vram_init_sizes(rdev); in r100_mc_init()
2835 base = rdev->mc.aper_base; in r100_mc_init()
2836 if (rdev->flags & RADEON_IS_IGP) in r100_mc_init()
2838 radeon_vram_location(rdev, &rdev->mc, base); in r100_mc_init()
2839 rdev->mc.gtt_base_align = 0; in r100_mc_init()
2840 if (!(rdev->flags & RADEON_IS_AGP)) in r100_mc_init()
2841 radeon_gtt_location(rdev, &rdev->mc); in r100_mc_init()
2842 radeon_update_bandwidth_info(rdev); in r100_mc_init()
2849 void r100_pll_errata_after_index(struct radeon_device *rdev) in r100_pll_errata_after_index() argument
2851 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { in r100_pll_errata_after_index()
2857 static void r100_pll_errata_after_data(struct radeon_device *rdev) in r100_pll_errata_after_data() argument
2862 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { in r100_pll_errata_after_data()
2871 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { in r100_pll_errata_after_data()
2882 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) in r100_pll_rreg() argument
2887 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2889 r100_pll_errata_after_index(rdev); in r100_pll_rreg()
2891 r100_pll_errata_after_data(rdev); in r100_pll_rreg()
2892 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2896 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in r100_pll_wreg() argument
2900 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2902 r100_pll_errata_after_index(rdev); in r100_pll_wreg()
2904 r100_pll_errata_after_data(rdev); in r100_pll_wreg()
2905 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2908 static void r100_set_safe_registers(struct radeon_device *rdev) in r100_set_safe_registers() argument
2910 if (ASIC_IS_RN50(rdev)) { in r100_set_safe_registers()
2911 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; in r100_set_safe_registers()
2912 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); in r100_set_safe_registers()
2913 } else if (rdev->family < CHIP_R200) { in r100_set_safe_registers()
2914 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; in r100_set_safe_registers()
2915 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); in r100_set_safe_registers()
2917 r200_set_safe_registers(rdev); in r100_set_safe_registers()
2929 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_rbbm_info() local
2950 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_cp_ring_info() local
2951 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_debugfs_cp_ring_info()
2955 radeon_ring_free_size(rdev, ring); in r100_debugfs_cp_ring_info()
2978 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_cp_csq_fifo() local
3028 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_mc_info() local
3068 int r100_debugfs_rbbm_init(struct radeon_device *rdev) in r100_debugfs_rbbm_init() argument
3071 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); in r100_debugfs_rbbm_init()
3077 int r100_debugfs_cp_init(struct radeon_device *rdev) in r100_debugfs_cp_init() argument
3080 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); in r100_debugfs_cp_init()
3086 int r100_debugfs_mc_info_init(struct radeon_device *rdev) in r100_debugfs_mc_info_init() argument
3089 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); in r100_debugfs_mc_info_init()
3095 int r100_set_surface_reg(struct radeon_device *rdev, int reg, in r100_set_surface_reg() argument
3102 if (rdev->family <= CHIP_RS200) { in r100_set_surface_reg()
3112 } else if (rdev->family <= CHIP_RV280) { in r100_set_surface_reg()
3130 if (rdev->family < CHIP_R300) in r100_set_surface_reg()
3143 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) in r100_clear_surface_reg() argument
3149 void r100_bandwidth_update(struct radeon_device *rdev) in r100_bandwidth_update() argument
3220 if (!rdev->mode_info.mode_config_initialized) in r100_bandwidth_update()
3223 radeon_update_display_priority(rdev); in r100_bandwidth_update()
3225 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update()
3226 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update()
3227 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; in r100_bandwidth_update()
3229 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_bandwidth_update()
3230 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update()
3231 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update()
3232 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; in r100_bandwidth_update()
3238 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { in r100_bandwidth_update()
3253 sclk_ff = rdev->pm.sclk; in r100_bandwidth_update()
3254 mclk_ff = rdev->pm.mclk; in r100_bandwidth_update()
3256 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); in r100_bandwidth_update()
3286 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ in r100_bandwidth_update()
3290 } else if (rdev->family == CHIP_R300 || in r100_bandwidth_update()
3291 rdev->family == CHIP_R350) { /* r300, r350 */ in r100_bandwidth_update()
3295 } else if (rdev->family == CHIP_RV350 || in r100_bandwidth_update()
3296 rdev->family <= CHIP_RV380) { in r100_bandwidth_update()
3301 } else if (rdev->family == CHIP_R420 || in r100_bandwidth_update()
3302 rdev->family == CHIP_R423 || in r100_bandwidth_update()
3303 rdev->family == CHIP_RV410) { in r100_bandwidth_update()
3327 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3328 if (rdev->family == CHIP_RS480) /* don't think rs400 */ in r100_bandwidth_update()
3335 if (rdev->family == CHIP_RS400 || in r100_bandwidth_update()
3336 rdev->family == CHIP_RS480) { in r100_bandwidth_update()
3343 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { in r100_bandwidth_update()
3364 if (rdev->family == CHIP_RV410 || in r100_bandwidth_update()
3365 rdev->family == CHIP_R420 || in r100_bandwidth_update()
3366 rdev->family == CHIP_R423) in r100_bandwidth_update()
3375 if (rdev->flags & RADEON_IS_AGP) { in r100_bandwidth_update()
3383 if (ASIC_IS_R300(rdev)) { in r100_bandwidth_update()
3386 if ((rdev->family == CHIP_RV100) || in r100_bandwidth_update()
3387 rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3388 if (rdev->mc.vram_is_ddr) in r100_bandwidth_update()
3393 if (rdev->mc.vram_width == 128) in r100_bandwidth_update()
3402 if (rdev->mc.vram_is_ddr) { in r100_bandwidth_update()
3403 if (rdev->mc.vram_width == 32) { in r100_bandwidth_update()
3430 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); in r100_bandwidth_update()
3452 if (ASIC_IS_RV100(rdev)) in r100_bandwidth_update()
3481 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3492 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3501 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3517 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3518 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3557 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3567 if ((rdev->family == CHIP_RS100) || in r100_bandwidth_update()
3568 (rdev->family == CHIP_RS200)) in r100_bandwidth_update()
3571 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; in r100_bandwidth_update()
3591 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3600 if (critical_point2 == 0 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3608 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3609 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3636 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in r100_ring_test() argument
3643 r = radeon_scratch_get(rdev, &scratch); in r100_ring_test()
3649 r = radeon_ring_lock(rdev, ring, 2); in r100_ring_test()
3652 radeon_scratch_free(rdev, scratch); in r100_ring_test()
3657 radeon_ring_unlock_commit(rdev, ring, false); in r100_ring_test()
3658 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ring_test()
3665 if (i < rdev->usec_timeout) { in r100_ring_test()
3672 radeon_scratch_free(rdev, scratch); in r100_ring_test()
3676 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in r100_ring_ib_execute() argument
3678 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_ring_ib_execute()
3691 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in r100_ib_test() argument
3699 r = radeon_scratch_get(rdev, &scratch); in r100_ib_test()
3705 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); in r100_ib_test()
3719 r = radeon_ib_schedule(rdev, &ib, NULL, false); in r100_ib_test()
3729 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ib_test()
3736 if (i < rdev->usec_timeout) { in r100_ib_test()
3744 radeon_ib_free(rdev, &ib); in r100_ib_test()
3746 radeon_scratch_free(rdev, scratch); in r100_ib_test()
3750 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) in r100_mc_stop() argument
3755 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_mc_stop()
3763 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3780 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3792 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) in r100_mc_resume() argument
3795 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3796 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3797 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3803 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3808 void r100_vga_render_disable(struct radeon_device *rdev) in r100_vga_render_disable() argument
3816 static void r100_debugfs(struct radeon_device *rdev) in r100_debugfs() argument
3820 r = r100_debugfs_mc_info_init(rdev); in r100_debugfs()
3822 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); in r100_debugfs()
3825 static void r100_mc_program(struct radeon_device *rdev) in r100_mc_program() argument
3830 r100_mc_stop(rdev, &save); in r100_mc_program()
3831 if (rdev->flags & RADEON_IS_AGP) { in r100_mc_program()
3833 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r100_mc_program()
3834 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r100_mc_program()
3835 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r100_mc_program()
3836 if (rdev->family > CHIP_RV200) in r100_mc_program()
3838 upper_32_bits(rdev->mc.agp_base) & 0xff); in r100_mc_program()
3842 if (rdev->family > CHIP_RV200) in r100_mc_program()
3846 if (r100_mc_wait_for_idle(rdev)) in r100_mc_program()
3847 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); in r100_mc_program()
3850 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r100_mc_program()
3851 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r100_mc_program()
3852 r100_mc_resume(rdev, &save); in r100_mc_program()
3855 static void r100_clock_startup(struct radeon_device *rdev) in r100_clock_startup() argument
3860 radeon_legacy_set_clock_gating(rdev, 1); in r100_clock_startup()
3864 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) in r100_clock_startup()
3869 static int r100_startup(struct radeon_device *rdev) in r100_startup() argument
3874 r100_set_common_regs(rdev); in r100_startup()
3876 r100_mc_program(rdev); in r100_startup()
3878 r100_clock_startup(rdev); in r100_startup()
3881 r100_enable_bm(rdev); in r100_startup()
3882 if (rdev->flags & RADEON_IS_PCI) { in r100_startup()
3883 r = r100_pci_gart_enable(rdev); in r100_startup()
3889 r = radeon_wb_init(rdev); in r100_startup()
3893 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r100_startup()
3895 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r100_startup()
3900 if (!rdev->irq.installed) { in r100_startup()
3901 r = radeon_irq_kms_init(rdev); in r100_startup()
3906 r100_irq_set(rdev); in r100_startup()
3907 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3909 r = r100_cp_init(rdev, 1024 * 1024); in r100_startup()
3911 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r100_startup()
3915 r = radeon_ib_pool_init(rdev); in r100_startup()
3917 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r100_startup()
3924 int r100_resume(struct radeon_device *rdev) in r100_resume() argument
3929 if (rdev->flags & RADEON_IS_PCI) in r100_resume()
3930 r100_pci_gart_disable(rdev); in r100_resume()
3932 r100_clock_startup(rdev); in r100_resume()
3934 if (radeon_asic_reset(rdev)) { in r100_resume()
3935 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r100_resume()
3940 radeon_combios_asic_init(rdev->ddev); in r100_resume()
3942 r100_clock_startup(rdev); in r100_resume()
3944 radeon_surface_init(rdev); in r100_resume()
3946 rdev->accel_working = true; in r100_resume()
3947 r = r100_startup(rdev); in r100_resume()
3949 rdev->accel_working = false; in r100_resume()
3954 int r100_suspend(struct radeon_device *rdev) in r100_suspend() argument
3956 radeon_pm_suspend(rdev); in r100_suspend()
3957 r100_cp_disable(rdev); in r100_suspend()
3958 radeon_wb_disable(rdev); in r100_suspend()
3959 r100_irq_disable(rdev); in r100_suspend()
3960 if (rdev->flags & RADEON_IS_PCI) in r100_suspend()
3961 r100_pci_gart_disable(rdev); in r100_suspend()
3965 void r100_fini(struct radeon_device *rdev) in r100_fini() argument
3967 radeon_pm_fini(rdev); in r100_fini()
3968 r100_cp_fini(rdev); in r100_fini()
3969 radeon_wb_fini(rdev); in r100_fini()
3970 radeon_ib_pool_fini(rdev); in r100_fini()
3971 radeon_gem_fini(rdev); in r100_fini()
3972 if (rdev->flags & RADEON_IS_PCI) in r100_fini()
3973 r100_pci_gart_fini(rdev); in r100_fini()
3974 radeon_agp_fini(rdev); in r100_fini()
3975 radeon_irq_kms_fini(rdev); in r100_fini()
3976 radeon_fence_driver_fini(rdev); in r100_fini()
3977 radeon_bo_fini(rdev); in r100_fini()
3978 radeon_atombios_fini(rdev); in r100_fini()
3979 kfree(rdev->bios); in r100_fini()
3980 rdev->bios = NULL; in r100_fini()
3990 void r100_restore_sanity(struct radeon_device *rdev) in r100_restore_sanity() argument
4008 int r100_init(struct radeon_device *rdev) in r100_init() argument
4013 r100_debugfs(rdev); in r100_init()
4015 r100_vga_render_disable(rdev); in r100_init()
4017 radeon_scratch_init(rdev); in r100_init()
4019 radeon_surface_init(rdev); in r100_init()
4021 r100_restore_sanity(rdev); in r100_init()
4024 if (!radeon_get_bios(rdev)) { in r100_init()
4025 if (ASIC_IS_AVIVO(rdev)) in r100_init()
4028 if (rdev->is_atom_bios) { in r100_init()
4029 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in r100_init()
4032 r = radeon_combios_init(rdev); in r100_init()
4037 if (radeon_asic_reset(rdev)) { in r100_init()
4038 dev_warn(rdev->dev, in r100_init()
4044 if (radeon_boot_test_post_card(rdev) == false) in r100_init()
4047 r100_errata(rdev); in r100_init()
4049 radeon_get_clock_info(rdev->ddev); in r100_init()
4051 if (rdev->flags & RADEON_IS_AGP) { in r100_init()
4052 r = radeon_agp_init(rdev); in r100_init()
4054 radeon_agp_disable(rdev); in r100_init()
4058 r100_mc_init(rdev); in r100_init()
4060 r = radeon_fence_driver_init(rdev); in r100_init()
4064 r = radeon_bo_init(rdev); in r100_init()
4067 if (rdev->flags & RADEON_IS_PCI) { in r100_init()
4068 r = r100_pci_gart_init(rdev); in r100_init()
4072 r100_set_safe_registers(rdev); in r100_init()
4075 radeon_pm_init(rdev); in r100_init()
4077 rdev->accel_working = true; in r100_init()
4078 r = r100_startup(rdev); in r100_init()
4081 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r100_init()
4082 r100_cp_fini(rdev); in r100_init()
4083 radeon_wb_fini(rdev); in r100_init()
4084 radeon_ib_pool_fini(rdev); in r100_init()
4085 radeon_irq_kms_fini(rdev); in r100_init()
4086 if (rdev->flags & RADEON_IS_PCI) in r100_init()
4087 r100_pci_gart_fini(rdev); in r100_init()
4088 rdev->accel_working = false; in r100_init()
4093 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) in r100_io_rreg() argument
4095 if (reg < rdev->rio_mem_size) in r100_io_rreg()
4096 return ioread32(rdev->rio_mem + reg); in r100_io_rreg()
4098 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_rreg()
4099 return ioread32(rdev->rio_mem + RADEON_MM_DATA); in r100_io_rreg()
4103 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r100_io_wreg() argument
4105 if (reg < rdev->rio_mem_size) in r100_io_wreg()
4106 iowrite32(v, rdev->rio_mem + reg); in r100_io_wreg()
4108 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_wreg()
4109 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); in r100_io_wreg()