841 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
842 	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |  in r100_ring_hdp_flush()
844 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r100_ring_hdp_flush()
845 	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);  in r100_ring_hdp_flush()
857 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
858 	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);  in r100_fence_ring_emit()
859 	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));  in r100_fence_ring_emit()
860 	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);  in r100_fence_ring_emit()
862 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_fence_ring_emit()
863 	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);  in r100_fence_ring_emit()
866 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r100_fence_ring_emit()
867 	radeon_ring_write(ring, fence->seq);  in r100_fence_ring_emit()
868 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r100_fence_ring_emit()
869 	radeon_ring_write(ring, RADEON_SW_INT_FIRE);  in r100_fence_ring_emit()
921 		radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));  in r100_copy_blit()
922 		radeon_ring_write(ring,  in r100_copy_blit()
934 		radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));  in r100_copy_blit()
935 		radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));  in r100_copy_blit()
936 		radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));  in r100_copy_blit()
937 		radeon_ring_write(ring, 0);  in r100_copy_blit()
938 		radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));  in r100_copy_blit()
939 		radeon_ring_write(ring, num_gpu_pages);  in r100_copy_blit()
940 		radeon_ring_write(ring, num_gpu_pages);  in r100_copy_blit()
941 		radeon_ring_write(ring, cur_pages | (stride_pixels << 16));  in r100_copy_blit()
943 	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));  in r100_copy_blit()
944 	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);  in r100_copy_blit()
945 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r100_copy_blit()
946 	radeon_ring_write(ring,  in r100_copy_blit()
982 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r100_ring_start()
983 	radeon_ring_write(ring,  in r100_ring_start()
3655 	radeon_ring_write(ring, PACKET0(scratch, 0));  in r100_ring_test()
3656 	radeon_ring_write(ring, 0xDEADBEEF);  in r100_ring_test()
3682 		radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));  in r100_ring_ib_execute()
3683 		radeon_ring_write(ring, next_rptr);  in r100_ring_ib_execute()
3686 	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));  in r100_ring_ib_execute()
3687 	radeon_ring_write(ring, ib->gpu_addr);  in r100_ring_ib_execute()
3688 	radeon_ring_write(ring, ib->length_dw);  in r100_ring_ib_execute()