210 	rdev->pm.dynpm_can_upclock = true;  in r100_pm_get_dynpm_state()
211 	rdev->pm.dynpm_can_downclock = true;  in r100_pm_get_dynpm_state()
213 	switch (rdev->pm.dynpm_planned_action) {  in r100_pm_get_dynpm_state()
215 		rdev->pm.requested_power_state_index = 0;  in r100_pm_get_dynpm_state()
216 		rdev->pm.dynpm_can_downclock = false;  in r100_pm_get_dynpm_state()
219 		if (rdev->pm.current_power_state_index == 0) {  in r100_pm_get_dynpm_state()
220 			rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;  in r100_pm_get_dynpm_state()
221 			rdev->pm.dynpm_can_downclock = false;  in r100_pm_get_dynpm_state()
223 			if (rdev->pm.active_crtc_count > 1) {  in r100_pm_get_dynpm_state()
224 				for (i = 0; i < rdev->pm.num_power_states; i++) {  in r100_pm_get_dynpm_state()
225 					if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)  in r100_pm_get_dynpm_state()
227 					else if (i >= rdev->pm.current_power_state_index) {  in r100_pm_get_dynpm_state()
228 						rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;  in r100_pm_get_dynpm_state()
231 						rdev->pm.requested_power_state_index = i;  in r100_pm_get_dynpm_state()
236 				rdev->pm.requested_power_state_index =  in r100_pm_get_dynpm_state()
237 					rdev->pm.current_power_state_index - 1;  in r100_pm_get_dynpm_state()
240 		if ((rdev->pm.active_crtc_count > 0) &&  in r100_pm_get_dynpm_state()
241 		    (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &  in r100_pm_get_dynpm_state()
243 			rdev->pm.requested_power_state_index++;  in r100_pm_get_dynpm_state()
247 		if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {  in r100_pm_get_dynpm_state()
248 			rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;  in r100_pm_get_dynpm_state()
249 			rdev->pm.dynpm_can_upclock = false;  in r100_pm_get_dynpm_state()
251 			if (rdev->pm.active_crtc_count > 1) {  in r100_pm_get_dynpm_state()
252 				for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {  in r100_pm_get_dynpm_state()
253 					if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)  in r100_pm_get_dynpm_state()
255 					else if (i <= rdev->pm.current_power_state_index) {  in r100_pm_get_dynpm_state()
256 						rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;  in r100_pm_get_dynpm_state()
259 						rdev->pm.requested_power_state_index = i;  in r100_pm_get_dynpm_state()
264 				rdev->pm.requested_power_state_index =  in r100_pm_get_dynpm_state()
265 					rdev->pm.current_power_state_index + 1;  in r100_pm_get_dynpm_state()
269 		rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;  in r100_pm_get_dynpm_state()
270 		rdev->pm.dynpm_can_upclock = false;  in r100_pm_get_dynpm_state()
278 	rdev->pm.requested_clock_mode_index = 0;  in r100_pm_get_dynpm_state()
281 		  rdev->pm.power_state[rdev->pm.requested_power_state_index].  in r100_pm_get_dynpm_state()
282 		  clock_info[rdev->pm.requested_clock_mode_index].sclk,  in r100_pm_get_dynpm_state()
283 		  rdev->pm.power_state[rdev->pm.requested_power_state_index].  in r100_pm_get_dynpm_state()
284 		  clock_info[rdev->pm.requested_clock_mode_index].mclk,  in r100_pm_get_dynpm_state()
285 		  rdev->pm.power_state[rdev->pm.requested_power_state_index].  in r100_pm_get_dynpm_state()
301 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
302 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
303 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
304 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
306 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
307 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;  in r100_pm_init_profile()
308 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
309 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
311 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
312 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;  in r100_pm_init_profile()
313 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
314 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
316 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
317 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
318 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
319 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
321 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
322 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
323 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
324 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
326 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
327 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
328 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
329 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
331 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;  in r100_pm_init_profile()
332 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in r100_pm_init_profile()
333 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;  in r100_pm_init_profile()
334 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;  in r100_pm_init_profile()
347 	int requested_index = rdev->pm.requested_power_state_index;  in r100_pm_misc()
348 	struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];  in r100_pm_misc()
427 	    rdev->asic->pm.set_pcie_lanes &&  in r100_pm_misc()
429 	     rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {  in r100_pm_misc()
783 				rdev->pm.vblank_sync = true;  in r100_irq_process()
792 				rdev->pm.vblank_sync = true;  in r100_irq_process()
3253 	sclk_ff = rdev->pm.sclk;  in r100_bandwidth_update()
3254 	mclk_ff = rdev->pm.mclk;  in r100_bandwidth_update()