Lines Matching refs:ring
1372 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1376 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3)); in cayman_cp_int_cntl_setup()
1386 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit() local
1387 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1392 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1393 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_fence_ring_emit()
1394 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1395 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1396 radeon_ring_write(ring, 10); /* poll interval */ in cayman_fence_ring_emit()
1398 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1399 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
1400 radeon_ring_write(ring, lower_32_bits(addr)); in cayman_fence_ring_emit()
1401 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1402 radeon_ring_write(ring, fence->seq); in cayman_fence_ring_emit()
1403 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1408 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute() local
1409 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cayman_ring_ib_execute()
1414 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1415 radeon_ring_write(ring, 1); in cayman_ring_ib_execute()
1417 if (ring->rptr_save_reg) { in cayman_ring_ib_execute()
1418 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; in cayman_ring_ib_execute()
1419 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1420 radeon_ring_write(ring, ((ring->rptr_save_reg - in cayman_ring_ib_execute()
1422 radeon_ring_write(ring, next_rptr); in cayman_ring_ib_execute()
1425 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1426 radeon_ring_write(ring, in cayman_ring_ib_execute()
1431 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1432 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in cayman_ring_ib_execute()
1435 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1436 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_ring_ib_execute()
1437 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_ring_ib_execute()
1438 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1439 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ in cayman_ring_ib_execute()
1451 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1456 struct radeon_ring *ring) in cayman_gfx_get_rptr() argument
1461 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1463 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_rptr()
1465 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_rptr()
1475 struct radeon_ring *ring) in cayman_gfx_get_wptr() argument
1479 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_wptr()
1481 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_wptr()
1490 struct radeon_ring *ring) in cayman_gfx_set_wptr() argument
1492 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cayman_gfx_set_wptr()
1493 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1495 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { in cayman_gfx_set_wptr()
1496 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1499 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1533 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start() local
1536 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1541 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1542 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1543 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1544 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1545 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in cayman_cp_start()
1546 radeon_ring_write(ring, 0); in cayman_cp_start()
1547 radeon_ring_write(ring, 0); in cayman_cp_start()
1548 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1552 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1559 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1560 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
1563 radeon_ring_write(ring, cayman_default_state[i]); in cayman_cp_start()
1565 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1566 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
1569 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
1570 radeon_ring_write(ring, 0); in cayman_cp_start()
1573 radeon_ring_write(ring, 0xc0026f00); in cayman_cp_start()
1574 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1575 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1576 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1579 radeon_ring_write(ring, 0xc0036f00); in cayman_cp_start()
1580 radeon_ring_write(ring, 0x00000bc4); in cayman_cp_start()
1581 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1582 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1583 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1585 radeon_ring_write(ring, 0xc0026900); in cayman_cp_start()
1586 radeon_ring_write(ring, 0x00000316); in cayman_cp_start()
1587 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cayman_cp_start()
1588 radeon_ring_write(ring, 0x00000010); /* */ in cayman_cp_start()
1590 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1599 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini() local
1601 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1602 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1642 struct radeon_ring *ring; in cayman_cp_resume() local
1674 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1675 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1690 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1691 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1696 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1699 ring->wptr = 0; in cayman_cp_resume()
1701 WREG32(cp_rb_wptr[i], ring->wptr); in cayman_cp_resume()
1709 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1710 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1711 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1713 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1715 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1716 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1717 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1967 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1974 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
1977 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
1982 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup() local
2042 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_startup()
2083 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2088 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2089 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2094 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2095 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2111 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_startup()
2112 if (ring->ring_size) { in cayman_startup()
2113 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cayman_startup()
2190 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init() local
2258 ring->ring_obj = NULL; in cayman_init()
2259 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2261 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2262 ring->ring_obj = NULL; in cayman_init()
2263 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2265 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2266 ring->ring_obj = NULL; in cayman_init()
2267 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2271 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_init()
2272 ring->ring_obj = NULL; in cayman_init()
2273 r600_ring_init(rdev, ring, 4096); in cayman_init()
2529 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2532 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
2533 radeon_ring_write(ring, pd_addr >> 12); in cayman_vm_flush()
2536 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2537 radeon_ring_write(ring, 0x1); in cayman_vm_flush()
2540 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
2541 radeon_ring_write(ring, 1 << vm_id); in cayman_vm_flush()
2544 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
2545 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in cayman_vm_flush()
2547 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cayman_vm_flush()
2548 radeon_ring_write(ring, 0); in cayman_vm_flush()
2549 radeon_ring_write(ring, 0); /* ref */ in cayman_vm_flush()
2550 radeon_ring_write(ring, 0); /* mask */ in cayman_vm_flush()
2551 radeon_ring_write(ring, 0x20); /* poll interval */ in cayman_vm_flush()
2554 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cayman_vm_flush()
2555 radeon_ring_write(ring, 0x0); in cayman_vm_flush()