718 	struct radeon_clock_voltage_dependency_table *table =  in kv_program_bootup_state()  local
721 	if (table && table->count) {  in kv_program_bootup_state()
723 			if (table->entries[i].clk == pi->boot_pl.sclk)  in kv_program_bootup_state()
730 		struct sumo_sclk_voltage_mapping_table *table =  in kv_program_bootup_state()  local
733 		if (table->num_max_dpm_entries == 0)  in kv_program_bootup_state()
737 			if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)  in kv_program_bootup_state()
820 	struct radeon_uvd_clock_voltage_dependency_table *table =  in kv_populate_uvd_table()  local
826 	if (table == NULL || table->count == 0)  in kv_populate_uvd_table()
830 	for (i = 0; i < table->count; i++) {  in kv_populate_uvd_table()
832 		    (pi->high_voltage_t < table->entries[i].v))  in kv_populate_uvd_table()
835 		pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);  in kv_populate_uvd_table()
836 		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);  in kv_populate_uvd_table()
837 		pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);  in kv_populate_uvd_table()
840 			(u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);  in kv_populate_uvd_table()
842 			(u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);  in kv_populate_uvd_table()
845 						     table->entries[i].vclk, false, &dividers);  in kv_populate_uvd_table()
851 						     table->entries[i].dclk, false, &dividers);  in kv_populate_uvd_table()
893 	struct radeon_vce_clock_voltage_dependency_table *table =  in kv_populate_vce_table()  local
897 	if (table == NULL || table->count == 0)  in kv_populate_vce_table()
901 	for (i = 0; i < table->count; i++) {  in kv_populate_vce_table()
903 		    pi->high_voltage_t < table->entries[i].v)  in kv_populate_vce_table()
906 		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);  in kv_populate_vce_table()
907 		pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_vce_table()
910 			(u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);  in kv_populate_vce_table()
913 						     table->entries[i].evclk, false, &dividers);  in kv_populate_vce_table()
954 	struct radeon_clock_voltage_dependency_table *table =  in kv_populate_samu_table()  local
960 	if (table == NULL || table->count == 0)  in kv_populate_samu_table()
964 	for (i = 0; i < table->count; i++) {  in kv_populate_samu_table()
966 		    pi->high_voltage_t < table->entries[i].v)  in kv_populate_samu_table()
969 		pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);  in kv_populate_samu_table()
970 		pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_samu_table()
973 			(u8)kv_get_clk_bypass(rdev, table->entries[i].clk);  in kv_populate_samu_table()
976 						     table->entries[i].clk, false, &dividers);  in kv_populate_samu_table()
1020 	struct radeon_clock_voltage_dependency_table *table =  in kv_populate_acp_table()  local
1026 	if (table == NULL || table->count == 0)  in kv_populate_acp_table()
1030 	for (i = 0; i < table->count; i++) {  in kv_populate_acp_table()
1031 		pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);  in kv_populate_acp_table()
1032 		pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_acp_table()
1035 						     table->entries[i].clk, false, &dividers);  in kv_populate_acp_table()
1079 	struct radeon_clock_voltage_dependency_table *table =  in kv_calculate_dfs_bypass_settings()  local
1082 	if (table && table->count) {  in kv_calculate_dfs_bypass_settings()
1085 				if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)  in kv_calculate_dfs_bypass_settings()
1087 				else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)  in kv_calculate_dfs_bypass_settings()
1089 				else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)  in kv_calculate_dfs_bypass_settings()
1091 				else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)  in kv_calculate_dfs_bypass_settings()
1093 				else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)  in kv_calculate_dfs_bypass_settings()
1102 		struct sumo_sclk_voltage_mapping_table *table =  in kv_calculate_dfs_bypass_settings()  local
1106 				if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)  in kv_calculate_dfs_bypass_settings()
1108 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)  in kv_calculate_dfs_bypass_settings()
1110 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)  in kv_calculate_dfs_bypass_settings()
1112 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)  in kv_calculate_dfs_bypass_settings()
1114 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)  in kv_calculate_dfs_bypass_settings()
1426 	struct radeon_uvd_clock_voltage_dependency_table *table =  in kv_update_uvd_dpm()  local
1432 		if (table->count)  in kv_update_uvd_dpm()
1433 			pi->uvd_boot_level = table->count - 1;  in kv_update_uvd_dpm()
1462 	struct radeon_vce_clock_voltage_dependency_table *table =  in kv_get_vce_boot_level()  local
1465 	for (i = 0; i < table->count; i++) {  in kv_get_vce_boot_level()
1466 		if (table->entries[i].evclk >= evclk)  in kv_get_vce_boot_level()
1478 	struct radeon_vce_clock_voltage_dependency_table *table =  in kv_update_vce_dpm()  local
1487 			pi->vce_boot_level = table->count - 1;  in kv_update_vce_dpm()
1519 	struct radeon_clock_voltage_dependency_table *table =  in kv_update_samu_dpm()  local
1525 			pi->samu_boot_level = table->count - 1;  in kv_update_samu_dpm()
1550 	struct radeon_clock_voltage_dependency_table *table =  in kv_get_acp_boot_level()  local
1553 	for (i = 0; i < table->count; i++) {  in kv_get_acp_boot_level()
1554 		if (table->entries[i].clk >= 0) /* XXX */  in kv_get_acp_boot_level()
1558 	if (i >= table->count)  in kv_get_acp_boot_level()
1559 		i = table->count - 1;  in kv_get_acp_boot_level()
1583 	struct radeon_clock_voltage_dependency_table *table =  in kv_update_acp_dpm()  local
1589 			pi->acp_boot_level = table->count - 1;  in kv_update_acp_dpm()
1711 	struct radeon_clock_voltage_dependency_table *table =  in kv_set_valid_clock_range()  local
1714 	if (table && table->count) {  in kv_set_valid_clock_range()
1716 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||  in kv_set_valid_clock_range()
1724 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)  in kv_set_valid_clock_range()
1730 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >  in kv_set_valid_clock_range()
1731 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))  in kv_set_valid_clock_range()
1737 		struct sumo_sclk_voltage_mapping_table *table =  in kv_set_valid_clock_range()  local
1741 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||  in kv_set_valid_clock_range()
1749 			if (table->entries[i].sclk_frequency <=  in kv_set_valid_clock_range()
1757 			     table->entries[pi->highest_valid].sclk_frequency) >  in kv_set_valid_clock_range()
1758 			    (table->entries[pi->lowest_valid].sclk_frequency -  in kv_set_valid_clock_range()
1967 						struct radeon_clock_and_voltage_limits *table)  in kv_construct_max_power_limits_table()  argument
1973 		table->sclk =  in kv_construct_max_power_limits_table()
1975 		table->vddc =  in kv_construct_max_power_limits_table()
1980 	table->mclk = pi->sys_info.nbp_memory_clock[0];  in kv_construct_max_power_limits_table()
2106 	struct radeon_clock_voltage_dependency_table *table =  in kv_get_high_voltage_limit()  local
2110 	if (table && table->count) {  in kv_get_high_voltage_limit()
2111 		for (i = table->count - 1; i >= 0; i--) {  in kv_get_high_voltage_limit()
2113 			    (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=  in kv_get_high_voltage_limit()
2120 		struct sumo_sclk_voltage_mapping_table *table =  in kv_get_high_voltage_limit()  local
2123 		for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {  in kv_get_high_voltage_limit()
2125 			    (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=  in kv_get_high_voltage_limit()
2147 	struct radeon_clock_voltage_dependency_table *table =  in kv_apply_state_adjust_rules()  local
2167 		for (i = table->count - 1; i >= 0; i++) {  in kv_apply_state_adjust_rules()
2168 			if (stable_p_state_sclk >= table->entries[i].clk) {  in kv_apply_state_adjust_rules()
2169 				stable_p_state_sclk = table->entries[i].clk;  in kv_apply_state_adjust_rules()
2175 			stable_p_state_sclk = table->entries[0].clk;  in kv_apply_state_adjust_rules()
2192 	if (table && table->count) {  in kv_apply_state_adjust_rules()
2198 				ps->levels[i].sclk = table->entries[limit].clk;  in kv_apply_state_adjust_rules()
2202 		struct sumo_sclk_voltage_mapping_table *table =  in kv_apply_state_adjust_rules()  local
2210 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;  in kv_apply_state_adjust_rules()
2351 	struct radeon_clock_voltage_dependency_table *table =  in kv_init_graphics_levels()  local
2354 	if (table && table->count) {  in kv_init_graphics_levels()
2358 		for (i = 0; i < table->count; i++) {  in kv_init_graphics_levels()
2361 			     kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))  in kv_init_graphics_levels()
2364 			kv_set_divider_value(rdev, i, table->entries[i].clk);  in kv_init_graphics_levels()
2367 							   table->entries[i].v);  in kv_init_graphics_levels()
2374 		struct sumo_sclk_voltage_mapping_table *table =  in kv_init_graphics_levels()  local
2378 		for (i = 0; i < table->num_max_dpm_entries; i++) {  in kv_init_graphics_levels()
2381 			    kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))  in kv_init_graphics_levels()
2384 			kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);  in kv_init_graphics_levels()
2385 			kv_set_vid(rdev, i, table->entries[i].vid_2bit);  in kv_init_graphics_levels()