Lines Matching refs:track
114 static void evergreen_cs_track_init(struct evergreen_cs_track *track) in evergreen_cs_track_init() argument
119 track->cb_color_fmask_bo[i] = NULL; in evergreen_cs_track_init()
120 track->cb_color_cmask_bo[i] = NULL; in evergreen_cs_track_init()
121 track->cb_color_cmask_slice[i] = 0; in evergreen_cs_track_init()
122 track->cb_color_fmask_slice[i] = 0; in evergreen_cs_track_init()
126 track->cb_color_bo[i] = NULL; in evergreen_cs_track_init()
127 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
128 track->cb_color_info[i] = 0; in evergreen_cs_track_init()
129 track->cb_color_view[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
130 track->cb_color_pitch[i] = 0; in evergreen_cs_track_init()
131 track->cb_color_slice[i] = 0xfffffff; in evergreen_cs_track_init()
132 track->cb_color_slice_idx[i] = 0; in evergreen_cs_track_init()
134 track->cb_target_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
135 track->cb_shader_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
136 track->cb_dirty = true; in evergreen_cs_track_init()
138 track->db_depth_slice = 0xffffffff; in evergreen_cs_track_init()
139 track->db_depth_view = 0xFFFFC000; in evergreen_cs_track_init()
140 track->db_depth_size = 0xFFFFFFFF; in evergreen_cs_track_init()
141 track->db_depth_control = 0xFFFFFFFF; in evergreen_cs_track_init()
142 track->db_z_info = 0xFFFFFFFF; in evergreen_cs_track_init()
143 track->db_z_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
144 track->db_z_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
145 track->db_z_read_bo = NULL; in evergreen_cs_track_init()
146 track->db_z_write_bo = NULL; in evergreen_cs_track_init()
147 track->db_s_info = 0xFFFFFFFF; in evergreen_cs_track_init()
148 track->db_s_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
149 track->db_s_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
150 track->db_s_read_bo = NULL; in evergreen_cs_track_init()
151 track->db_s_write_bo = NULL; in evergreen_cs_track_init()
152 track->db_dirty = true; in evergreen_cs_track_init()
153 track->htile_bo = NULL; in evergreen_cs_track_init()
154 track->htile_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
155 track->htile_surface = 0; in evergreen_cs_track_init()
158 track->vgt_strmout_size[i] = 0; in evergreen_cs_track_init()
159 track->vgt_strmout_bo[i] = NULL; in evergreen_cs_track_init()
160 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
162 track->streamout_dirty = true; in evergreen_cs_track_init()
163 track->sx_misc_kill_all_prims = false; in evergreen_cs_track_init()
201 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned() local
204 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
206 surf->base_align = track->group_size; in evergreen_surface_check_linear_aligned()
223 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d() local
226 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
229 surf->base_align = track->group_size; in evergreen_surface_check_1d()
236 track->group_size, surf->bpe, surf->nsamples); in evergreen_surface_check_1d()
254 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d() local
265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
392 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb() local
398 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; in evergreen_cs_track_validate_cb()
399 pitch = track->cb_color_pitch[id]; in evergreen_cs_track_validate_cb()
400 slice = track->cb_color_slice[id]; in evergreen_cs_track_validate_cb()
403 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
404 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
405 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
406 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
407 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
408 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
409 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
415 id, track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
427 __func__, __LINE__, id, track->cb_color_pitch[id], in evergreen_cs_track_validate_cb()
428 track->cb_color_slice[id], track->cb_color_attrib[id], in evergreen_cs_track_validate_cb()
429 track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
433 offset = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
441 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
454 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
455 tmp = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
469 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
478 track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()
479 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
495 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile() local
498 if (track->htile_bo == NULL) { in evergreen_cs_track_validate_htile()
500 __func__, __LINE__, track->db_z_info); in evergreen_cs_track_validate_htile()
504 if (G_028ABC_LINEAR(track->htile_surface)) { in evergreen_cs_track_validate_htile()
508 nby = round_up(nby, track->npipes * 8); in evergreen_cs_track_validate_htile()
514 switch (track->npipes) { in evergreen_cs_track_validate_htile()
537 __func__, __LINE__, track->npipes); in evergreen_cs_track_validate_htile()
545 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in evergreen_cs_track_validate_htile()
546 size += track->htile_offset; in evergreen_cs_track_validate_htile()
548 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
550 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
559 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil() local
565 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_stencil()
566 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_stencil()
567 slice = track->db_depth_slice; in evergreen_cs_track_validate_stencil()
570 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_stencil()
571 surf.format = G_028044_FORMAT(track->db_s_info); in evergreen_cs_track_validate_stencil()
572 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); in evergreen_cs_track_validate_stencil()
573 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_stencil()
574 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_stencil()
575 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_stencil()
576 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_stencil()
602 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
603 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
608 offset = track->db_s_read_offset << 8; in evergreen_cs_track_validate_stencil()
615 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
619 (unsigned long)track->db_s_read_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
620 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
622 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
623 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
627 offset = track->db_s_write_offset << 8; in evergreen_cs_track_validate_stencil()
634 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
638 (unsigned long)track->db_s_write_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
639 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
644 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_stencil()
656 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth() local
662 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_depth()
663 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_depth()
664 slice = track->db_depth_slice; in evergreen_cs_track_validate_depth()
667 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_depth()
668 surf.format = G_028040_FORMAT(track->db_z_info); in evergreen_cs_track_validate_depth()
669 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); in evergreen_cs_track_validate_depth()
670 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_depth()
671 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_depth()
672 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_depth()
673 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_depth()
693 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
694 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
701 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
702 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
706 offset = track->db_z_read_offset << 8; in evergreen_cs_track_validate_depth()
713 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
717 (unsigned long)track->db_z_read_offset << 8, mslice, in evergreen_cs_track_validate_depth()
718 radeon_bo_size(track->db_z_read_bo)); in evergreen_cs_track_validate_depth()
722 offset = track->db_z_write_offset << 8; in evergreen_cs_track_validate_depth()
729 if (offset > radeon_bo_size(track->db_z_write_bo)) { in evergreen_cs_track_validate_depth()
733 (unsigned long)track->db_z_write_offset << 8, mslice, in evergreen_cs_track_validate_depth()
734 radeon_bo_size(track->db_z_write_bo)); in evergreen_cs_track_validate_depth()
739 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_depth()
930 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check() local
936 if (track->streamout_dirty && track->vgt_strmout_config) { in evergreen_cs_track_check()
938 if (track->vgt_strmout_config & (1 << i)) { in evergreen_cs_track_check()
939 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; in evergreen_cs_track_check()
945 if (track->vgt_strmout_bo[i]) { in evergreen_cs_track_check()
946 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in evergreen_cs_track_check()
947 (u64)track->vgt_strmout_size[i]; in evergreen_cs_track_check()
948 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in evergreen_cs_track_check()
951 radeon_bo_size(track->vgt_strmout_bo[i])); in evergreen_cs_track_check()
960 track->streamout_dirty = false; in evergreen_cs_track_check()
963 if (track->sx_misc_kill_all_prims) in evergreen_cs_track_check()
968 if (track->cb_dirty) { in evergreen_cs_track_check()
969 tmp = track->cb_target_mask; in evergreen_cs_track_check()
971 u32 format = G_028C70_FORMAT(track->cb_color_info[i]); in evergreen_cs_track_check()
976 if (track->cb_color_bo[i] == NULL) { in evergreen_cs_track_check()
978 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in evergreen_cs_track_check()
988 track->cb_dirty = false; in evergreen_cs_track_check()
991 if (track->db_dirty) { in evergreen_cs_track_check()
993 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID && in evergreen_cs_track_check()
994 G_028800_STENCIL_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1000 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID && in evergreen_cs_track_check()
1001 G_028800_Z_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1006 track->db_dirty = false; in evergreen_cs_track_check()
1097 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_check_reg() local
1172 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1173 track->db_dirty = true; in evergreen_cs_check_reg()
1190 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1199 track->db_z_info &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_check_reg()
1201 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1208 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1215 track->db_dirty = true; in evergreen_cs_check_reg()
1218 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1219 track->db_dirty = true; in evergreen_cs_check_reg()
1222 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1223 track->db_dirty = true; in evergreen_cs_check_reg()
1226 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1227 track->db_dirty = true; in evergreen_cs_check_reg()
1230 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1231 track->db_dirty = true; in evergreen_cs_check_reg()
1240 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1242 track->db_z_read_bo = reloc->robj; in evergreen_cs_check_reg()
1243 track->db_dirty = true; in evergreen_cs_check_reg()
1252 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1254 track->db_z_write_bo = reloc->robj; in evergreen_cs_check_reg()
1255 track->db_dirty = true; in evergreen_cs_check_reg()
1264 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1266 track->db_s_read_bo = reloc->robj; in evergreen_cs_check_reg()
1267 track->db_dirty = true; in evergreen_cs_check_reg()
1276 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1278 track->db_s_write_bo = reloc->robj; in evergreen_cs_check_reg()
1279 track->db_dirty = true; in evergreen_cs_check_reg()
1282 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1283 track->streamout_dirty = true; in evergreen_cs_check_reg()
1286 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1287 track->streamout_dirty = true; in evergreen_cs_check_reg()
1300 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_check_reg()
1302 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1303 track->streamout_dirty = true; in evergreen_cs_check_reg()
1311 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_check_reg()
1312 track->streamout_dirty = true; in evergreen_cs_check_reg()
1323 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1324 track->cb_dirty = true; in evergreen_cs_check_reg()
1327 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1328 track->cb_dirty = true; in evergreen_cs_check_reg()
1337 track->nsamples = 1 << tmp; in evergreen_cs_check_reg()
1346 track->nsamples = 1 << tmp; in evergreen_cs_check_reg()
1357 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1358 track->cb_dirty = true; in evergreen_cs_check_reg()
1365 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1366 track->cb_dirty = true; in evergreen_cs_check_reg()
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1386 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1388 track->cb_dirty = true; in evergreen_cs_check_reg()
1395 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1404 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1406 track->cb_dirty = true; in evergreen_cs_check_reg()
1417 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1418 track->cb_dirty = true; in evergreen_cs_check_reg()
1425 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1426 track->cb_dirty = true; in evergreen_cs_check_reg()
1437 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1438 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_check_reg()
1439 track->cb_dirty = true; in evergreen_cs_check_reg()
1446 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1447 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_check_reg()
1448 track->cb_dirty = true; in evergreen_cs_check_reg()
1471 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1479 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1480 track->cb_dirty = true; in evergreen_cs_check_reg()
1499 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1507 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1508 track->cb_dirty = true; in evergreen_cs_check_reg()
1525 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1542 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1553 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1564 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1581 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1583 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1584 track->cb_dirty = true; in evergreen_cs_check_reg()
1597 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1599 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1600 track->cb_dirty = true; in evergreen_cs_check_reg()
1609 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1611 track->htile_bo = reloc->robj; in evergreen_cs_check_reg()
1612 track->db_dirty = true; in evergreen_cs_check_reg()
1616 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1619 track->db_dirty = true; in evergreen_cs_check_reg()
1758 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_check_reg()
1797 struct evergreen_cs_track *track; in evergreen_packet3_check() local
1805 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
2044 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2066 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2068 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2387 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_packet3_check()
2637 struct evergreen_cs_track *track; in evergreen_cs_parse() local
2641 if (p->track == NULL) { in evergreen_cs_parse()
2643 track = kzalloc(sizeof(*track), GFP_KERNEL); in evergreen_cs_parse()
2644 if (track == NULL) in evergreen_cs_parse()
2646 evergreen_cs_track_init(track); in evergreen_cs_parse()
2654 track->npipes = 1; in evergreen_cs_parse()
2658 track->npipes = 2; in evergreen_cs_parse()
2661 track->npipes = 4; in evergreen_cs_parse()
2664 track->npipes = 8; in evergreen_cs_parse()
2670 track->nbanks = 4; in evergreen_cs_parse()
2674 track->nbanks = 8; in evergreen_cs_parse()
2677 track->nbanks = 16; in evergreen_cs_parse()
2683 track->group_size = 256; in evergreen_cs_parse()
2687 track->group_size = 512; in evergreen_cs_parse()
2693 track->row_size = 1; in evergreen_cs_parse()
2697 track->row_size = 2; in evergreen_cs_parse()
2700 track->row_size = 4; in evergreen_cs_parse()
2704 p->track = track; in evergreen_cs_parse()
2709 kfree(p->track); in evergreen_cs_parse()
2710 p->track = NULL; in evergreen_cs_parse()
2725 kfree(p->track); in evergreen_cs_parse()
2726 p->track = NULL; in evergreen_cs_parse()
2730 kfree(p->track); in evergreen_cs_parse()
2731 p->track = NULL; in evergreen_cs_parse()
2741 kfree(p->track); in evergreen_cs_parse()
2742 p->track = NULL; in evergreen_cs_parse()