2758 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2813 			r = r600_dma_cs_next_reloc(p, &src_reloc);  in evergreen_dma_cs_parse()
2831 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2833 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2842 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2844 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2854 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
2864 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2865 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2871 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2873 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2890 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2892 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2901 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2903 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2913 				ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2914 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2934 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2936 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2951 				ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2954 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2974 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2976 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2991 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2992 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3005 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3011 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3012 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3036 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3038 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3053 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3054 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3065 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3075 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3076 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3082 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3084 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3101 				ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3123 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3125 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3140 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3141 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()