2762 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2827 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2828 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2831 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2833 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2852 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2853 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2862 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2863 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2871 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2873 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2886 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2887 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2890 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2892 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2932 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
2933 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2934 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2936 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2972 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
2973 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2974 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2976 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3034 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3035 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3036 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3038 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3063 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3064 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3073 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3074 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3082 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3084 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3121 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3122 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3123 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3125 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()