Lines Matching refs:reloc
1098 struct radeon_bo_list *reloc; in evergreen_cs_check_reg() local
1163 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1169 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1192 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1200 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1201 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1202 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1205 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_check_reg()
1234 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1241 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1242 track->db_z_read_bo = reloc->robj; in evergreen_cs_check_reg()
1246 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1253 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1254 track->db_z_write_bo = reloc->robj; in evergreen_cs_check_reg()
1258 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1265 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1266 track->db_s_read_bo = reloc->robj; in evergreen_cs_check_reg()
1270 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1277 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1278 track->db_s_write_bo = reloc->robj; in evergreen_cs_check_reg()
1293 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1302 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1315 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1321 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1379 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1386 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1397 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1403 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1404 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1458 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1465 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1468 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_check_reg()
1486 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1493 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1496 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_check_reg()
1519 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1524 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1525 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1536 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1541 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1542 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1574 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1582 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1583 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1590 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1598 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1599 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_check_reg()
1603 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1610 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1611 track->htile_bo = reloc->robj; in evergreen_cs_check_reg()
1721 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1727 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1735 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1741 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1749 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1755 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1796 struct radeon_bo_list *reloc; in evergreen_packet3_check() local
1834 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1840 offset = reloc->gpu_offset + in evergreen_packet3_check()
1880 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1886 offset = reloc->gpu_offset + in evergreen_packet3_check()
1915 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1921 offset = reloc->gpu_offset + in evergreen_packet3_check()
1943 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1949 offset = reloc->gpu_offset + in evergreen_packet3_check()
2038 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2044 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2046 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2047 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2095 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2100 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2116 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2122 offset = reloc->gpu_offset + in evergreen_packet3_check()
2170 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2179 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2181 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2183 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2208 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2217 offset = reloc->gpu_offset + tmp; in evergreen_packet3_check()
2219 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2221 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2242 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2247 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2258 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2263 offset = reloc->gpu_offset + in evergreen_packet3_check()
2279 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2285 offset = reloc->gpu_offset + in evergreen_packet3_check()
2301 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2307 offset = reloc->gpu_offset + in evergreen_packet3_check()
2368 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2375 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_packet3_check()
2376 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
2379 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_packet3_check()
2390 texture = reloc->robj; in evergreen_packet3_check()
2391 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2405 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2410 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2411 mipmap = reloc->robj; in evergreen_packet3_check()
2424 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2431 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2434 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2437 offset64 = reloc->gpu_offset + offset; in evergreen_packet3_check()
2506 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2513 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2515 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2518 offset += reloc->gpu_offset; in evergreen_packet3_check()
2525 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2532 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2534 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2537 offset += reloc->gpu_offset; in evergreen_packet3_check()
2550 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2561 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2563 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2566 offset += reloc->gpu_offset; in evergreen_packet3_check()
2579 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2586 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2588 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2591 offset += reloc->gpu_offset; in evergreen_packet3_check()
2603 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2610 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2612 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2615 offset += reloc->gpu_offset; in evergreen_packet3_check()